+/* clrpsw: clrpsw $uimm8 */
+
+static SEM_PC
+SEM_FN_NAME (m32rbf,clrpsw) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_clrpsw.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ USI opval = ANDSI (GET_H_CR (((UINT) 0)), ORSI (ZEXTQISI (INVQI (FLD (f_uimm8))), 65280));
+ SET_H_CR (((UINT) 0), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* setpsw: setpsw $uimm8 */
+
+static SEM_PC
+SEM_FN_NAME (m32rbf,setpsw) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_clrpsw.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ USI opval = FLD (f_uimm8);
+ SET_H_CR (((UINT) 0), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* bset: bset $uimm3,@($slo16,$sr) */
+
+static SEM_PC
+SEM_FN_NAME (m32rbf,bset) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bset.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ QI opval = ORQI (GETMEMQI (current_cpu, pc, ADDSI (* FLD (i_sr), FLD (f_simm16))), SLLQI (1, SUBSI (7, FLD (f_uimm3))));
+ SETMEMQI (current_cpu, pc, ADDSI (* FLD (i_sr), FLD (f_simm16)), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* bclr: bclr $uimm3,@($slo16,$sr) */
+
+static SEM_PC
+SEM_FN_NAME (m32rbf,bclr) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bset.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ QI opval = ANDQI (GETMEMQI (current_cpu, pc, ADDSI (* FLD (i_sr), FLD (f_simm16))), INVQI (SLLQI (1, SUBSI (7, FLD (f_uimm3)))));
+ SETMEMQI (current_cpu, pc, ADDSI (* FLD (i_sr), FLD (f_simm16)), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* btst: btst $uimm3,$sr */
+
+static SEM_PC
+SEM_FN_NAME (m32rbf,btst) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bset.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ BI opval = ANDQI (SRLQI (* FLD (i_sr), SUBSI (7, FLD (f_uimm3))), 1);
+ CPU (h_cond) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "cond", 'x', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* Table of all semantic fns. */
+
+static const struct sem_fn_desc sem_fns[] = {
+ { M32RBF_INSN_X_INVALID, SEM_FN_NAME (m32rbf,x_invalid) },
+ { M32RBF_INSN_X_AFTER, SEM_FN_NAME (m32rbf,x_after) },
+ { M32RBF_INSN_X_BEFORE, SEM_FN_NAME (m32rbf,x_before) },
+ { M32RBF_INSN_X_CTI_CHAIN, SEM_FN_NAME (m32rbf,x_cti_chain) },
+ { M32RBF_INSN_X_CHAIN, SEM_FN_NAME (m32rbf,x_chain) },
+ { M32RBF_INSN_X_BEGIN, SEM_FN_NAME (m32rbf,x_begin) },
+ { M32RBF_INSN_ADD, SEM_FN_NAME (m32rbf,add) },
+ { M32RBF_INSN_ADD3, SEM_FN_NAME (m32rbf,add3) },
+ { M32RBF_INSN_AND, SEM_FN_NAME (m32rbf,and) },
+ { M32RBF_INSN_AND3, SEM_FN_NAME (m32rbf,and3) },
+ { M32RBF_INSN_OR, SEM_FN_NAME (m32rbf,or) },
+ { M32RBF_INSN_OR3, SEM_FN_NAME (m32rbf,or3) },
+ { M32RBF_INSN_XOR, SEM_FN_NAME (m32rbf,xor) },
+ { M32RBF_INSN_XOR3, SEM_FN_NAME (m32rbf,xor3) },
+ { M32RBF_INSN_ADDI, SEM_FN_NAME (m32rbf,addi) },
+ { M32RBF_INSN_ADDV, SEM_FN_NAME (m32rbf,addv) },
+ { M32RBF_INSN_ADDV3, SEM_FN_NAME (m32rbf,addv3) },
+ { M32RBF_INSN_ADDX, SEM_FN_NAME (m32rbf,addx) },
+ { M32RBF_INSN_BC8, SEM_FN_NAME (m32rbf,bc8) },
+ { M32RBF_INSN_BC24, SEM_FN_NAME (m32rbf,bc24) },
+ { M32RBF_INSN_BEQ, SEM_FN_NAME (m32rbf,beq) },
+ { M32RBF_INSN_BEQZ, SEM_FN_NAME (m32rbf,beqz) },
+ { M32RBF_INSN_BGEZ, SEM_FN_NAME (m32rbf,bgez) },
+ { M32RBF_INSN_BGTZ, SEM_FN_NAME (m32rbf,bgtz) },
+ { M32RBF_INSN_BLEZ, SEM_FN_NAME (m32rbf,blez) },
+ { M32RBF_INSN_BLTZ, SEM_FN_NAME (m32rbf,bltz) },
+ { M32RBF_INSN_BNEZ, SEM_FN_NAME (m32rbf,bnez) },
+ { M32RBF_INSN_BL8, SEM_FN_NAME (m32rbf,bl8) },
+ { M32RBF_INSN_BL24, SEM_FN_NAME (m32rbf,bl24) },
+ { M32RBF_INSN_BNC8, SEM_FN_NAME (m32rbf,bnc8) },
+ { M32RBF_INSN_BNC24, SEM_FN_NAME (m32rbf,bnc24) },
+ { M32RBF_INSN_BNE, SEM_FN_NAME (m32rbf,bne) },
+ { M32RBF_INSN_BRA8, SEM_FN_NAME (m32rbf,bra8) },
+ { M32RBF_INSN_BRA24, SEM_FN_NAME (m32rbf,bra24) },
+ { M32RBF_INSN_CMP, SEM_FN_NAME (m32rbf,cmp) },
+ { M32RBF_INSN_CMPI, SEM_FN_NAME (m32rbf,cmpi) },
+ { M32RBF_INSN_CMPU, SEM_FN_NAME (m32rbf,cmpu) },
+ { M32RBF_INSN_CMPUI, SEM_FN_NAME (m32rbf,cmpui) },
+ { M32RBF_INSN_DIV, SEM_FN_NAME (m32rbf,div) },
+ { M32RBF_INSN_DIVU, SEM_FN_NAME (m32rbf,divu) },
+ { M32RBF_INSN_REM, SEM_FN_NAME (m32rbf,rem) },
+ { M32RBF_INSN_REMU, SEM_FN_NAME (m32rbf,remu) },
+ { M32RBF_INSN_JL, SEM_FN_NAME (m32rbf,jl) },
+ { M32RBF_INSN_JMP, SEM_FN_NAME (m32rbf,jmp) },
+ { M32RBF_INSN_LD, SEM_FN_NAME (m32rbf,ld) },
+ { M32RBF_INSN_LD_D, SEM_FN_NAME (m32rbf,ld_d) },
+ { M32RBF_INSN_LDB, SEM_FN_NAME (m32rbf,ldb) },
+ { M32RBF_INSN_LDB_D, SEM_FN_NAME (m32rbf,ldb_d) },
+ { M32RBF_INSN_LDH, SEM_FN_NAME (m32rbf,ldh) },
+ { M32RBF_INSN_LDH_D, SEM_FN_NAME (m32rbf,ldh_d) },
+ { M32RBF_INSN_LDUB, SEM_FN_NAME (m32rbf,ldub) },
+ { M32RBF_INSN_LDUB_D, SEM_FN_NAME (m32rbf,ldub_d) },
+ { M32RBF_INSN_LDUH, SEM_FN_NAME (m32rbf,lduh) },
+ { M32RBF_INSN_LDUH_D, SEM_FN_NAME (m32rbf,lduh_d) },
+ { M32RBF_INSN_LD_PLUS, SEM_FN_NAME (m32rbf,ld_plus) },
+ { M32RBF_INSN_LD24, SEM_FN_NAME (m32rbf,ld24) },
+ { M32RBF_INSN_LDI8, SEM_FN_NAME (m32rbf,ldi8) },
+ { M32RBF_INSN_LDI16, SEM_FN_NAME (m32rbf,ldi16) },
+ { M32RBF_INSN_LOCK, SEM_FN_NAME (m32rbf,lock) },
+ { M32RBF_INSN_MACHI, SEM_FN_NAME (m32rbf,machi) },
+ { M32RBF_INSN_MACLO, SEM_FN_NAME (m32rbf,maclo) },
+ { M32RBF_INSN_MACWHI, SEM_FN_NAME (m32rbf,macwhi) },
+ { M32RBF_INSN_MACWLO, SEM_FN_NAME (m32rbf,macwlo) },
+ { M32RBF_INSN_MUL, SEM_FN_NAME (m32rbf,mul) },
+ { M32RBF_INSN_MULHI, SEM_FN_NAME (m32rbf,mulhi) },
+ { M32RBF_INSN_MULLO, SEM_FN_NAME (m32rbf,mullo) },
+ { M32RBF_INSN_MULWHI, SEM_FN_NAME (m32rbf,mulwhi) },
+ { M32RBF_INSN_MULWLO, SEM_FN_NAME (m32rbf,mulwlo) },
+ { M32RBF_INSN_MV, SEM_FN_NAME (m32rbf,mv) },
+ { M32RBF_INSN_MVFACHI, SEM_FN_NAME (m32rbf,mvfachi) },
+ { M32RBF_INSN_MVFACLO, SEM_FN_NAME (m32rbf,mvfaclo) },
+ { M32RBF_INSN_MVFACMI, SEM_FN_NAME (m32rbf,mvfacmi) },
+ { M32RBF_INSN_MVFC, SEM_FN_NAME (m32rbf,mvfc) },
+ { M32RBF_INSN_MVTACHI, SEM_FN_NAME (m32rbf,mvtachi) },
+ { M32RBF_INSN_MVTACLO, SEM_FN_NAME (m32rbf,mvtaclo) },
+ { M32RBF_INSN_MVTC, SEM_FN_NAME (m32rbf,mvtc) },
+ { M32RBF_INSN_NEG, SEM_FN_NAME (m32rbf,neg) },
+ { M32RBF_INSN_NOP, SEM_FN_NAME (m32rbf,nop) },
+ { M32RBF_INSN_NOT, SEM_FN_NAME (m32rbf,not) },
+ { M32RBF_INSN_RAC, SEM_FN_NAME (m32rbf,rac) },
+ { M32RBF_INSN_RACH, SEM_FN_NAME (m32rbf,rach) },
+ { M32RBF_INSN_RTE, SEM_FN_NAME (m32rbf,rte) },
+ { M32RBF_INSN_SETH, SEM_FN_NAME (m32rbf,seth) },
+ { M32RBF_INSN_SLL, SEM_FN_NAME (m32rbf,sll) },
+ { M32RBF_INSN_SLL3, SEM_FN_NAME (m32rbf,sll3) },
+ { M32RBF_INSN_SLLI, SEM_FN_NAME (m32rbf,slli) },
+ { M32RBF_INSN_SRA, SEM_FN_NAME (m32rbf,sra) },
+ { M32RBF_INSN_SRA3, SEM_FN_NAME (m32rbf,sra3) },
+ { M32RBF_INSN_SRAI, SEM_FN_NAME (m32rbf,srai) },
+ { M32RBF_INSN_SRL, SEM_FN_NAME (m32rbf,srl) },
+ { M32RBF_INSN_SRL3, SEM_FN_NAME (m32rbf,srl3) },
+ { M32RBF_INSN_SRLI, SEM_FN_NAME (m32rbf,srli) },
+ { M32RBF_INSN_ST, SEM_FN_NAME (m32rbf,st) },
+ { M32RBF_INSN_ST_D, SEM_FN_NAME (m32rbf,st_d) },
+ { M32RBF_INSN_STB, SEM_FN_NAME (m32rbf,stb) },
+ { M32RBF_INSN_STB_D, SEM_FN_NAME (m32rbf,stb_d) },
+ { M32RBF_INSN_STH, SEM_FN_NAME (m32rbf,sth) },
+ { M32RBF_INSN_STH_D, SEM_FN_NAME (m32rbf,sth_d) },
+ { M32RBF_INSN_ST_PLUS, SEM_FN_NAME (m32rbf,st_plus) },
+ { M32RBF_INSN_ST_MINUS, SEM_FN_NAME (m32rbf,st_minus) },
+ { M32RBF_INSN_SUB, SEM_FN_NAME (m32rbf,sub) },
+ { M32RBF_INSN_SUBV, SEM_FN_NAME (m32rbf,subv) },
+ { M32RBF_INSN_SUBX, SEM_FN_NAME (m32rbf,subx) },
+ { M32RBF_INSN_TRAP, SEM_FN_NAME (m32rbf,trap) },
+ { M32RBF_INSN_UNLOCK, SEM_FN_NAME (m32rbf,unlock) },
+ { M32RBF_INSN_CLRPSW, SEM_FN_NAME (m32rbf,clrpsw) },
+ { M32RBF_INSN_SETPSW, SEM_FN_NAME (m32rbf,setpsw) },
+ { M32RBF_INSN_BSET, SEM_FN_NAME (m32rbf,bset) },
+ { M32RBF_INSN_BCLR, SEM_FN_NAME (m32rbf,bclr) },
+ { M32RBF_INSN_BTST, SEM_FN_NAME (m32rbf,btst) },
+ { 0, 0 }
+};
+
+/* Add the semantic fns to IDESC_TABLE. */
+
+void
+SEM_FN_NAME (m32rbf,init_idesc_table) (SIM_CPU *current_cpu)
+{
+ IDESC *idesc_table = CPU_IDESC (current_cpu);
+ const struct sem_fn_desc *sf;
+ int mach_num = MACH_NUM (CPU_MACH (current_cpu));
+
+ for (sf = &sem_fns[0]; sf->fn != 0; ++sf)
+ {
+ const CGEN_INSN *insn = idesc_table[sf->index].idata;
+ int valid_p = (CGEN_INSN_VIRTUAL_P (insn)
+ || CGEN_INSN_MACH_HAS_P (insn, mach_num));
+#if FAST_P
+ if (valid_p)
+ idesc_table[sf->index].sem_fast = sf->fn;
+ else
+ idesc_table[sf->index].sem_fast = SEM_FN_NAME (m32rbf,x_invalid);
+#else
+ if (valid_p)
+ idesc_table[sf->index].sem_full = sf->fn;
+ else
+ idesc_table[sf->index].sem_full = SEM_FN_NAME (m32rbf,x_invalid);
+#endif
+ }
+}
+