- sim_io_printf(sd,"Prefetch(%d,0x%s,0x%s,%d,%d);\n",CCA,pr_addr(pAddr),pr_addr(vAddr),DATA,hint);
-#endif /* DEBUG */
-
- /* For our simple memory model we do nothing */
- return;
-}
-
-/* Description from page A-22 of the "MIPS IV Instruction Set" manual
- (revision 3.1) */
-/* Load a value from memory. Use the cache and main memory as
- specified in the Cache Coherence Algorithm (CCA) and the sort of
- access (IorD) to find the contents of AccessLength memory bytes
- starting at physical location pAddr. The data is returned in the
- fixed width naturally-aligned memory element (MemElem). The
- low-order two (or three) bits of the address and the AccessLength
- indicate which of the bytes within MemElem needs to be given to the
- processor. If the memory access type of the reference is uncached
- then only the referenced bytes are read from memory and valid
- within the memory element. If the access type is cached, and the
- data is not present in cache, an implementation specific size and
- alignment block of memory is read and loaded into the cache to
- satisfy a load reference. At a minimum, the block is the entire
- memory element. */
-void
-load_memory (SIM_DESC sd,
- sim_cpu *cpu,
- address_word cia,
- uword64* memvalp,
- uword64* memval1p,
- int CCA,
- int AccessLength,
- address_word pAddr,
- address_word vAddr,
- int IorD)
-{
- uword64 value = 0;
- uword64 value1 = 0;
-
-#ifdef DEBUG
- sim_io_printf(sd,"DBG: LoadMemory(%p,%p,%d,%d,0x%s,0x%s,%s)\n",memvalp,memval1p,CCA,AccessLength,pr_addr(pAddr),pr_addr(vAddr),(IorD ? "isDATA" : "isINSTRUCTION"));
-#endif /* DEBUG */
-
-#if defined(WARN_MEM)
- if (CCA != uncached)
- sim_io_eprintf(sd,"LoadMemory CCA (%d) is not uncached (currently all accesses treated as cached)\n",CCA);
-#endif /* WARN_MEM */
-
- /* If instruction fetch then we need to check that the two lo-order
- bits are zero, otherwise raise a InstructionFetch exception: */
- if ((IorD == isINSTRUCTION)
- && ((pAddr & 0x3) != 0)
- && (((pAddr & 0x1) != 0) || ((vAddr & 0x1) == 0)))
- SignalExceptionInstructionFetch ();
-
- if (((pAddr & LOADDRMASK) + AccessLength) > LOADDRMASK)
- {
- /* In reality this should be a Bus Error */
- sim_io_error (sd, "AccessLength of %d would extend over %dbit aligned boundary for physical address 0x%s\n",
- AccessLength,
- (LOADDRMASK + 1) << 2,
- pr_addr (pAddr));
- }
-
-#if defined(TRACE)
- dotrace (SD, CPU, tracefh,((IorD == isDATA) ? 0 : 2),(unsigned int)(pAddr&0xFFFFFFFF),(AccessLength + 1),"load%s",((IorD == isDATA) ? "" : " instruction"));
-#endif /* TRACE */
-
- /* Read the specified number of bytes from memory. Adjust for
- host/target byte ordering/ Align the least significant byte
- read. */
-
- switch (AccessLength)
- {
- case AccessLength_QUADWORD :
- {
- unsigned_16 val = sim_core_read_aligned_16 (cpu, NULL_CIA,
- sim_core_read_map, pAddr);
- value1 = VH8_16 (val);
- value = VL8_16 (val);
- break;
- }
- case AccessLength_DOUBLEWORD :
- value = sim_core_read_aligned_8 (cpu, NULL_CIA,
- sim_core_read_map, pAddr);
- break;
- case AccessLength_SEPTIBYTE :
- value = sim_core_read_misaligned_7 (cpu, NULL_CIA,
- sim_core_read_map, pAddr);
- case AccessLength_SEXTIBYTE :
- value = sim_core_read_misaligned_6 (cpu, NULL_CIA,
- sim_core_read_map, pAddr);
- case AccessLength_QUINTIBYTE :
- value = sim_core_read_misaligned_5 (cpu, NULL_CIA,
- sim_core_read_map, pAddr);
- case AccessLength_WORD :
- value = sim_core_read_aligned_4 (cpu, NULL_CIA,
- sim_core_read_map, pAddr);
- break;
- case AccessLength_TRIPLEBYTE :
- value = sim_core_read_misaligned_3 (cpu, NULL_CIA,
- sim_core_read_map, pAddr);
- case AccessLength_HALFWORD :
- value = sim_core_read_aligned_2 (cpu, NULL_CIA,
- sim_core_read_map, pAddr);
- break;
- case AccessLength_BYTE :
- value = sim_core_read_aligned_1 (cpu, NULL_CIA,
- sim_core_read_map, pAddr);
- break;
- default:
- abort ();
- }
-
-#ifdef DEBUG
- printf("DBG: LoadMemory() : (offset %d) : value = 0x%s%s\n",
- (int)(pAddr & LOADDRMASK),pr_uword64(value1),pr_uword64(value));
-#endif /* DEBUG */
-
- /* See also store_memory. */
- if (AccessLength <= AccessLength_DOUBLEWORD)
- {
- if (BigEndianMem)
- /* for big endian target, byte (pAddr&LOADDRMASK == 0) is
- shifted to the most significant byte position. */
- value <<= (((7 - (pAddr & LOADDRMASK)) - AccessLength) * 8);
- else
- /* For little endian target, byte (pAddr&LOADDRMASK == 0)
- is already in the correct postition. */
- value <<= ((pAddr & LOADDRMASK) * 8);
- }
-
-#ifdef DEBUG
- printf("DBG: LoadMemory() : shifted value = 0x%s%s\n",
- pr_uword64(value1),pr_uword64(value));
-#endif /* DEBUG */
-
- *memvalp = value;
- if (memval1p) *memval1p = value1;
-}
-
-
-/* Description from page A-23 of the "MIPS IV Instruction Set" manual
- (revision 3.1) */
-/* Store a value to memory. The specified data is stored into the
- physical location pAddr using the memory hierarchy (data caches and
- main memory) as specified by the Cache Coherence Algorithm
- (CCA). The MemElem contains the data for an aligned, fixed-width
- memory element (word for 32-bit processors, doubleword for 64-bit
- processors), though only the bytes that will actually be stored to
- memory need to be valid. The low-order two (or three) bits of pAddr
- and the AccessLength field indicates which of the bytes within the
- MemElem data should actually be stored; only these bytes in memory
- will be changed. */
-
-void
-store_memory (SIM_DESC sd,
- sim_cpu *cpu,
- address_word cia,
- int CCA,
- int AccessLength,
- uword64 MemElem,
- uword64 MemElem1, /* High order 64 bits */
- address_word pAddr,
- address_word vAddr)
-{
-#ifdef DEBUG
- sim_io_printf(sd,"DBG: StoreMemory(%d,%d,0x%s,0x%s,0x%s,0x%s)\n",CCA,AccessLength,pr_uword64(MemElem),pr_uword64(MemElem1),pr_addr(pAddr),pr_addr(vAddr));
-#endif /* DEBUG */
-
-#if defined(WARN_MEM)
- if (CCA != uncached)
- sim_io_eprintf(sd,"StoreMemory CCA (%d) is not uncached (currently all accesses treated as cached)\n",CCA);
-#endif /* WARN_MEM */
-
- if (((pAddr & LOADDRMASK) + AccessLength) > LOADDRMASK)
- sim_io_error(sd,"AccessLength of %d would extend over %dbit aligned boundary for physical address 0x%s\n",AccessLength,(LOADDRMASK + 1)<<2,pr_addr(pAddr));
-
-#if defined(TRACE)
- dotrace (SD, CPU, tracefh,1,(unsigned int)(pAddr&0xFFFFFFFF),(AccessLength + 1),"store");
-#endif /* TRACE */
-
-#ifdef DEBUG
- printf("DBG: StoreMemory: offset = %d MemElem = 0x%s%s\n",(unsigned int)(pAddr & LOADDRMASK),pr_uword64(MemElem1),pr_uword64(MemElem));
-#endif /* DEBUG */
-
- /* See also load_memory */
- if (AccessLength <= AccessLength_DOUBLEWORD)
- {
- if (BigEndianMem)
- /* for big endian target, byte (pAddr&LOADDRMASK == 0) is
- shifted to the most significant byte position. */
- MemElem >>= (((7 - (pAddr & LOADDRMASK)) - AccessLength) * 8);
- else
- /* For little endian target, byte (pAddr&LOADDRMASK == 0)
- is already in the correct postition. */
- MemElem >>= ((pAddr & LOADDRMASK) * 8);
- }
-
-#ifdef DEBUG
- printf("DBG: StoreMemory: shift = %d MemElem = 0x%s%s\n",shift,pr_uword64(MemElem1),pr_uword64(MemElem));
-#endif /* DEBUG */
-
- switch (AccessLength)
- {
- case AccessLength_QUADWORD :
- {
- unsigned_16 val = U16_8 (MemElem1, MemElem);
- sim_core_write_aligned_16 (cpu, NULL_CIA,
- sim_core_write_map, pAddr, val);
- break;
- }
- case AccessLength_DOUBLEWORD :
- sim_core_write_aligned_8 (cpu, NULL_CIA,
- sim_core_write_map, pAddr, MemElem);
- break;
- case AccessLength_SEPTIBYTE :
- sim_core_write_misaligned_7 (cpu, NULL_CIA,
- sim_core_write_map, pAddr, MemElem);
- break;
- case AccessLength_SEXTIBYTE :
- sim_core_write_misaligned_6 (cpu, NULL_CIA,
- sim_core_write_map, pAddr, MemElem);
- break;
- case AccessLength_QUINTIBYTE :
- sim_core_write_misaligned_5 (cpu, NULL_CIA,
- sim_core_write_map, pAddr, MemElem);
- break;
- case AccessLength_WORD :
- sim_core_write_aligned_4 (cpu, NULL_CIA,
- sim_core_write_map, pAddr, MemElem);
- break;
- case AccessLength_TRIPLEBYTE :
- sim_core_write_misaligned_3 (cpu, NULL_CIA,
- sim_core_write_map, pAddr, MemElem);
- break;
- case AccessLength_HALFWORD :
- sim_core_write_aligned_2 (cpu, NULL_CIA,
- sim_core_write_map, pAddr, MemElem);
- break;
- case AccessLength_BYTE :
- sim_core_write_aligned_1 (cpu, NULL_CIA,
- sim_core_write_map, pAddr, MemElem);
- break;
- default:
- abort ();
- }
-
- return;
-}
-
-
-unsigned32
-ifetch32 (SIM_DESC sd,
- sim_cpu *cpu,
- address_word cia,
- address_word vaddr)
-{
- /* Copy the action of the LW instruction */
- address_word reverse = (ReverseEndian ? (LOADDRMASK >> 2) : 0);
- address_word bigend = (BigEndianCPU ? (LOADDRMASK >> 2) : 0);
- unsigned64 value;
- address_word paddr;
- unsigned32 instruction;
- unsigned byte;
- int cca;
- AddressTranslation (vaddr, isINSTRUCTION, isLOAD, &paddr, &cca, isTARGET, isREAL);
- paddr = ((paddr & ~LOADDRMASK) | ((paddr & LOADDRMASK) ^ (reverse << 2)));
- LoadMemory (&value, NULL, cca, AccessLength_WORD, paddr, vaddr, isINSTRUCTION, isREAL);
- byte = ((vaddr & LOADDRMASK) ^ (bigend << 2));
- instruction = ((value >> (8 * byte)) & 0xFFFFFFFF);
- return instruction;
-}
-
-
-/* Description from page A-26 of the "MIPS IV Instruction Set" manual (revision 3.1) */
-/* Order loads and stores to synchronise shared memory. Perform the
- action necessary to make the effects of groups of synchronizable
- loads and stores indicated by stype occur in the same order for all
- processors. */
-void
-sync_operation (SIM_DESC sd,
- sim_cpu *cpu,
- address_word cia,
- int stype)
-{
-#ifdef DEBUG
- sim_io_printf(sd,"SyncOperation(%d) : TODO\n",stype);
-#endif /* DEBUG */
- return;
-}
-
-/* Description from page A-26 of the "MIPS IV Instruction Set" manual (revision 3.1) */
-/* Signal an exception condition. This will result in an exception
- that aborts the instruction. The instruction operation pseudocode
- will never see a return from this function call. */
-
-void
-signal_exception (SIM_DESC sd,
- sim_cpu *cpu,
- address_word cia,
- int exception,...)
-{
- int vector;
-
-#ifdef DEBUG
- sim_io_printf(sd,"DBG: SignalException(%d) PC = 0x%s\n",exception,pr_addr(cia));