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Automatic date update in version.in
[deliverable/binutils-gdb.git]
/
sim
/
mips
/
micromips.igen
diff --git
a/sim/mips/micromips.igen
b/sim/mips/micromips.igen
index 2c62376da9ae87e7d941ca383778f677b8417c4f..bddea52e7bd44caee11a6b8d454de8ff6c84a571 100644
(file)
--- a/
sim/mips/micromips.igen
+++ b/
sim/mips/micromips.igen
@@
-1,5
+1,5
@@
// Simulator definition for the micromips ASE.
// Simulator definition for the micromips ASE.
-// Copyright (C) 2005-20
15
Free Software Foundation, Inc.
+// Copyright (C) 2005-20
20
Free Software Foundation, Inc.
// Contributed by Imagination Technologies, Ltd.
// Written by Andrew Bennett <andrew.bennett@imgtec.com>
//
// Contributed by Imagination Technologies, Ltd.
// Written by Andrew Bennett <andrew.bennett@imgtec.com>
//
@@
-39,6
+39,9
@@
:compute:::int:IMM_SHIFT_2BIT:IMMEDIATE:(IMMEDIATE << 2)
:function:::address_word:delayslot_micromips:address_word target, address_word nia, int delayslot_instruction_size
:compute:::int:IMM_SHIFT_2BIT:IMMEDIATE:(IMMEDIATE << 2)
:function:::address_word:delayslot_micromips:address_word target, address_word nia, int delayslot_instruction_size
+*micromips32:
+*micromips64:
+*micromipsdsp:
{
instruction_word delay_insn;
sim_events_slip (SD, 1);
{
instruction_word delay_insn;
sim_events_slip (SD, 1);
@@
-52,12
+55,16
@@
}
:function:::address_word:process_isa_mode:address_word target
}
:function:::address_word:process_isa_mode:address_word target
+*micromips32:
+*micromips64:
{
SD->isa_mode = target & 0x1;
{
SD->isa_mode = target & 0x1;
- return (target & (-
1 << 1
));
+ return (target & (-
(1 << 1)
));
}
:function:::address_word:do_micromips_jalr:int rt, int rs, address_word nia, int delayslot_instruction_size
}
:function:::address_word:do_micromips_jalr:int rt, int rs, address_word nia, int delayslot_instruction_size
+*micromips32:
+*micromips64:
{
GPR[rt] = (nia + delayslot_instruction_size) | ISA_MODE_MICROMIPS;
return (process_isa_mode (SD_,
{
GPR[rt] = (nia + delayslot_instruction_size) | ISA_MODE_MICROMIPS;
return (process_isa_mode (SD_,
@@
-65,6
+72,8
@@
}
:function:::address_word:do_micromips_jal:address_word target, address_word nia, int delayslot_instruction_size
}
:function:::address_word:do_micromips_jal:address_word target, address_word nia, int delayslot_instruction_size
+*micromips32:
+*micromips64:
{
RA = (nia + delayslot_instruction_size) | ISA_MODE_MICROMIPS;
return delayslot_micromips (SD_, target, nia, delayslot_instruction_size);
{
RA = (nia + delayslot_instruction_size) | ISA_MODE_MICROMIPS;
return delayslot_micromips (SD_, target, nia, delayslot_instruction_size);
@@
-72,6
+81,8
@@
:function:::unsigned32:compute_movep_src_reg:int reg
:function:::unsigned32:compute_movep_src_reg:int reg
+*micromips32:
+*micromips64:
{
switch(reg)
{
{
switch(reg)
{
@@
-88,6
+99,8
@@
}
:function:::unsigned32:compute_andi16_imm:int encoded_imm
}
:function:::unsigned32:compute_andi16_imm:int encoded_imm
+*micromips32:
+*micromips64:
{
switch (encoded_imm)
{
{
switch (encoded_imm)
{
@@
-112,6
+125,8
@@
}
:function:::FP_formats:convert_fmt_micromips:int fmt
}
:function:::FP_formats:convert_fmt_micromips:int fmt
+*micromips32:
+*micromips64:
{
switch (fmt)
{
{
switch (fmt)
{
@@
-123,6
+138,8
@@
}
:function:::FP_formats:convert_fmt_micromips_cvt_d:int fmt
}
:function:::FP_formats:convert_fmt_micromips_cvt_d:int fmt
+*micromips32:
+*micromips64:
{
switch (fmt)
{
{
switch (fmt)
{
@@
-135,6
+152,8
@@
:function:::FP_formats:convert_fmt_micromips_cvt_s:int fmt
:function:::FP_formats:convert_fmt_micromips_cvt_s:int fmt
+*micromips32:
+*micromips64:
{
switch (fmt)
{
{
switch (fmt)
{
@@
-845,11
+864,8
@@
address_word base = GPR[BASE];
address_word offset = EXTEND12 (IMMEDIATE);
address_word vaddr = loadstore_ea (SD_, base, offset);
address_word base = GPR[BASE];
address_word offset = EXTEND12 (IMMEDIATE);
address_word vaddr = loadstore_ea (SD_, base, offset);
- address_word paddr;
- int uncached;
- if (AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached,
- isTARGET, isREAL))
- CacheOp (OP, vaddr, paddr, instruction_0);
+ address_word paddr = vaddr;
+ CacheOp (OP, vaddr, paddr, instruction_0);
}
}
@@
-2255,6
+2271,8
@@
:%s::::FMT_MICROMIPS:int fmt
:%s::::FMT_MICROMIPS:int fmt
+*micromips32:
+*micromips64:
{
switch (fmt)
{
{
switch (fmt)
{
@@
-2267,6
+2285,8
@@
:%s::::FMT_MICROMIPS_CVT_D:int fmt
:%s::::FMT_MICROMIPS_CVT_D:int fmt
+*micromips32:
+*micromips64:
{
switch (fmt)
{
{
switch (fmt)
{
@@
-2279,6
+2299,8
@@
:%s::::FMT_MICROMIPS_CVT_S:int fmt
:%s::::FMT_MICROMIPS_CVT_S:int fmt
+*micromips32:
+*micromips64:
{
switch (fmt)
{
{
switch (fmt)
{
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