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2004-05-11 Maciej W. Rozycki <macro@ds2.pg.gda.pl>
[deliverable/binutils-gdb.git]
/
sim
/
mips
/
sim-main.c
diff --git
a/sim/mips/sim-main.c
b/sim/mips/sim-main.c
index 48a37ae8ec43d6f988ebf7384f3443f4b00e3b87..edee498bc94c2ac494e018b8a463241d0081467a 100644
(file)
--- a/
sim/mips/sim-main.c
+++ b/
sim/mips/sim-main.c
@@
-163,44
+163,36
@@
load_memory (SIM_DESC SD,
switch (AccessLength)
{
switch (AccessLength)
{
- case AccessLength_QUADWORD
:
+ case AccessLength_QUADWORD:
{
{
- unsigned_16 val = sim_core_read_aligned_16 (CPU,
NULL_CIA
, read_map, pAddr);
+ unsigned_16 val = sim_core_read_aligned_16 (CPU,
cia
, read_map, pAddr);
value1 = VH8_16 (val);
value = VL8_16 (val);
break;
}
value1 = VH8_16 (val);
value = VL8_16 (val);
break;
}
- case AccessLength_DOUBLEWORD :
- value = sim_core_read_aligned_8 (CPU, NULL_CIA,
- read_map, pAddr);
+ case AccessLength_DOUBLEWORD:
+ value = sim_core_read_aligned_8 (CPU, cia, read_map, pAddr);
break;
break;
- case AccessLength_SEPTIBYTE :
- value = sim_core_read_misaligned_7 (CPU, NULL_CIA,
- read_map, pAddr);
+ case AccessLength_SEPTIBYTE:
+ value = sim_core_read_misaligned_7 (CPU, cia, read_map, pAddr);
break;
break;
- case AccessLength_SEXTIBYTE :
- value = sim_core_read_misaligned_6 (CPU, NULL_CIA,
- read_map, pAddr);
+ case AccessLength_SEXTIBYTE:
+ value = sim_core_read_misaligned_6 (CPU, cia, read_map, pAddr);
break;
break;
- case AccessLength_QUINTIBYTE :
- value = sim_core_read_misaligned_5 (CPU, NULL_CIA,
- read_map, pAddr);
+ case AccessLength_QUINTIBYTE:
+ value = sim_core_read_misaligned_5 (CPU, cia, read_map, pAddr);
break;
break;
- case AccessLength_WORD :
- value = sim_core_read_aligned_4 (CPU, NULL_CIA,
- read_map, pAddr);
+ case AccessLength_WORD:
+ value = sim_core_read_aligned_4 (CPU, cia, read_map, pAddr);
break;
break;
- case AccessLength_TRIPLEBYTE :
- value = sim_core_read_misaligned_3 (CPU, NULL_CIA,
- read_map, pAddr);
+ case AccessLength_TRIPLEBYTE:
+ value = sim_core_read_misaligned_3 (CPU, cia, read_map, pAddr);
break;
break;
- case AccessLength_HALFWORD :
- value = sim_core_read_aligned_2 (CPU, NULL_CIA,
- read_map, pAddr);
+ case AccessLength_HALFWORD:
+ value = sim_core_read_aligned_2 (CPU, cia, read_map, pAddr);
break;
break;
- case AccessLength_BYTE :
- value = sim_core_read_aligned_1 (CPU, NULL_CIA,
- read_map, pAddr);
+ case AccessLength_BYTE:
+ value = sim_core_read_aligned_1 (CPU, cia, read_map, pAddr);
break;
default:
abort ();
break;
default:
abort ();
@@
-300,43
+292,35
@@
store_memory (SIM_DESC SD,
switch (AccessLength)
{
switch (AccessLength)
{
- case AccessLength_QUADWORD
:
+ case AccessLength_QUADWORD:
{
unsigned_16 val = U16_8 (MemElem1, MemElem);
{
unsigned_16 val = U16_8 (MemElem1, MemElem);
- sim_core_write_aligned_16 (CPU,
NULL_CIA
, write_map, pAddr, val);
+ sim_core_write_aligned_16 (CPU,
cia
, write_map, pAddr, val);
break;
}
break;
}
- case AccessLength_DOUBLEWORD :
- sim_core_write_aligned_8 (CPU, NULL_CIA,
- write_map, pAddr, MemElem);
+ case AccessLength_DOUBLEWORD:
+ sim_core_write_aligned_8 (CPU, cia, write_map, pAddr, MemElem);
break;
break;
- case AccessLength_SEPTIBYTE :
- sim_core_write_misaligned_7 (CPU, NULL_CIA,
- write_map, pAddr, MemElem);
+ case AccessLength_SEPTIBYTE:
+ sim_core_write_misaligned_7 (CPU, cia, write_map, pAddr, MemElem);
break;
break;
- case AccessLength_SEXTIBYTE :
- sim_core_write_misaligned_6 (CPU, NULL_CIA,
- write_map, pAddr, MemElem);
+ case AccessLength_SEXTIBYTE:
+ sim_core_write_misaligned_6 (CPU, cia, write_map, pAddr, MemElem);
break;
break;
- case AccessLength_QUINTIBYTE :
- sim_core_write_misaligned_5 (CPU, NULL_CIA,
- write_map, pAddr, MemElem);
+ case AccessLength_QUINTIBYTE:
+ sim_core_write_misaligned_5 (CPU, cia, write_map, pAddr, MemElem);
break;
break;
- case AccessLength_WORD :
- sim_core_write_aligned_4 (CPU, NULL_CIA,
- write_map, pAddr, MemElem);
+ case AccessLength_WORD:
+ sim_core_write_aligned_4 (CPU, cia, write_map, pAddr, MemElem);
break;
break;
- case AccessLength_TRIPLEBYTE :
- sim_core_write_misaligned_3 (CPU, NULL_CIA,
- write_map, pAddr, MemElem);
+ case AccessLength_TRIPLEBYTE:
+ sim_core_write_misaligned_3 (CPU, cia, write_map, pAddr, MemElem);
break;
break;
- case AccessLength_HALFWORD :
- sim_core_write_aligned_2 (CPU, NULL_CIA,
- write_map, pAddr, MemElem);
+ case AccessLength_HALFWORD:
+ sim_core_write_aligned_2 (CPU, cia, write_map, pAddr, MemElem);
break;
break;
- case AccessLength_BYTE :
- sim_core_write_aligned_1 (CPU, NULL_CIA,
- write_map, pAddr, MemElem);
+ case AccessLength_BYTE:
+ sim_core_write_aligned_1 (CPU, cia, write_map, pAddr, MemElem);
break;
default:
abort ();
break;
default:
abort ();
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