* common/aclocal.m4: Pass ../../intl to ZW_GNU_GETTEXT_SISTER_DIR.

[deliverable/binutils-gdb.git] / sim / mips / sim-main.h

diff --git a/sim/mips/sim-main.h b/sim/mips/sim-main.h
index 8087a3a3f8e37f0d96d6bdd5e1c45d99616caaf6..76e6374e01dcc7962683b7f4ad73af66e51e83d1 100644 (file)
--- a/sim/mips/sim-main.h
+++ b/sim/mips/sim-main.h
@@ -1,5 +1,5 @@
 /* MIPS Simulator definition.
 /* MIPS Simulator definition.

-   Copyright (C) 1997, 1998 Free Software Foundation, Inc.
+   Copyright (C) 1997, 1998, 2003 Free Software Foundation, Inc.

    Contributed by Cygnus Support.
 
 This file is part of GDB, the GNU debugger.
    Contributed by Cygnus Support.
 
 This file is part of GDB, the GNU debugger.


@@ -41,7 +41,7 @@ mips_core_signal ((SD), (CPU), (CIA), (MAP), (NR_BYTES), (ADDR), (TRANSFER), (ER
 typedef address_word sim_cia;
 
 #include "sim-base.h"
 typedef address_word sim_cia;
 
 #include "sim-base.h"

-
+#include "bfd.h"

 
 /* Deprecated macros and types for manipulating 64bit values.  Use
    ../common/sim-bits.h and ../common/sim-endian.h macros instead. */
 
 /* Deprecated macros and types for manipulating 64bit values.  Use
    ../common/sim-bits.h and ../common/sim-endian.h macros instead. */


@@ -64,6 +64,7 @@ typedef unsigned64 uword64;
 /* Floating-point operations: */
 
 #include "sim-fpu.h"
 /* Floating-point operations: */
 
 #include "sim-fpu.h"

+#include "cp1.h"

 
 /* FPU registers must be one of the following types. All other values
    are reserved (and undefined). */
 
 /* FPU registers must be one of the following types. All other values
    are reserved (and undefined). */


@@ -72,6 +73,7 @@ typedef enum {
  fmt_double  = 1,
  fmt_word    = 4,
  fmt_long    = 5,
  fmt_double  = 1,
  fmt_word    = 4,
  fmt_long    = 5,

+ fmt_ps      = 6,

  /* The following are well outside the normal acceptable format
     range, and are used in the register status vector. */
  fmt_unknown       = 0x10000000,
  /* The following are well outside the normal acceptable format
     range, and are used in the register status vector. */
  fmt_unknown       = 0x10000000,


@@ -80,16 +82,9 @@ typedef enum {
  fmt_uninterpreted_64 = 0x80000000U,
 } FP_formats;
 
  fmt_uninterpreted_64 = 0x80000000U,
 } FP_formats;
 

-/* Macro to update FPSR condition-code field. This is complicated by
-   the fact that there is a hole in the index range of the bits within
-   the FCSR register. Also, the number of bits visible depends on the
-   MIPS ISA version being supported. */
-
-#define SETFCC(cc,v) {\
-  int bit = ((cc == 0) ? 23 : (24 + (cc)));\
-  FCSR = ((FCSR & ~(1 << bit)) | ((v) << bit));\
-}
-#define GETFCC(cc) (((((cc) == 0) ? (FCSR & (1 << 23)) : (FCSR & (1 << (24 + (cc))))) != 0) ? 1U : 0)
+/* For paired word (pw) operations, the opcode representation is fmt_word,
+   but register transfers (StoreFPR, ValueFPR, etc.) are done as fmt_long.  */
+#define fmt_pw fmt_long

 
 /* This should be the COC1 value at the start of the preceding
    instruction: */
 
 /* This should be the COC1 value at the start of the preceding
    instruction: */


@@ -104,36 +99,6 @@ typedef enum {
 #define SizeFGR() (WITH_TARGET_FLOATING_POINT_BITSIZE)
 #endif
 
 #define SizeFGR() (WITH_TARGET_FLOATING_POINT_BITSIZE)
 #endif
 

-/* Standard FCRS bits: */
-#define IR (0) /* Inexact Result */
-#define UF (1) /* UnderFlow */
-#define OF (2) /* OverFlow */
-#define DZ (3) /* Division by Zero */
-#define IO (4) /* Invalid Operation */
-#define UO (5) /* Unimplemented Operation */
-
-/* Get masks for individual flags: */
-#if 1 /* SAFE version */
-#define FP_FLAGS(b)  (((unsigned)(b) < 5) ? (1 << ((b) + 2)) : 0)
-#define FP_ENABLE(b) (((unsigned)(b) < 5) ? (1 << ((b) + 7)) : 0)
-#define FP_CAUSE(b)  (((unsigned)(b) < 6) ? (1 << ((b) + 12)) : 0)
-#else
-#define FP_FLAGS(b)  (1 << ((b) + 2))
-#define FP_ENABLE(b) (1 << ((b) + 7))
-#define FP_CAUSE(b)  (1 << ((b) + 12))
-#endif
-
-#define FP_FS         (1 << 24) /* MIPS III onwards : Flush to Zero */
-
-#define FP_MASK_RM    (0x3)
-#define FP_SH_RM      (0)
-#define FP_RM_NEAREST (0) /* Round to nearest        (Round) */
-#define FP_RM_TOZERO  (1) /* Round to zero           (Trunc) */
-#define FP_RM_TOPINF  (2) /* Round to Plus infinity  (Ceil) */
-#define FP_RM_TOMINF  (3) /* Round to Minus infinity (Floor) */
-#define GETRM()       (int)((FCSR >> FP_SH_RM) & FP_MASK_RM)
-
-

 
 
 
 
 
 


@@ -254,10 +219,10 @@ memset (&(CPU)->pending, 0, sizeof ((CPU)->pending))
 /* For backward compatibility */
 #define PENDING_FILL(R,VAL)                                            \
 do {                                                                   \
 /* For backward compatibility */
 #define PENDING_FILL(R,VAL)                                            \
 do {                                                                   \

-  if ((R) >= FGRIDX && (R) < FGRIDX + NR_FGR)                          \
+  if ((R) >= FGR_BASE && (R) < FGR_BASE + NR_FGR)                      \

     {                                                                  \
     {                                                                  \

-      PENDING_SCHED(FGR[(R) - FGRIDX], VAL, 1, -1);                    \
-      PENDING_SCHED(FPR_STATE[(R) - FGRIDX], fmt_uninterpreted, 1, -1);        \
+      PENDING_SCHED(FGR[(R) - FGR_BASE], VAL, 1, -1);                  \
+      PENDING_SCHED(FPR_STATE[(R) - FGR_BASE], fmt_uninterpreted, 1, -1); \

     }                                                                  \
   else                                                                 \
     PENDING_SCHED(GPR[(R)], VAL, 1, -1);                               \
     }                                                                  \
   else                                                                 \
     PENDING_SCHED(GPR[(R)], VAL, 1, -1);                               \


@@ -347,10 +312,12 @@ struct _sim_cpu {
    state. */
 
 #ifndef TM_MIPS_H
    state. */
 
 #ifndef TM_MIPS_H

-#define LAST_EMBED_REGNUM (89)
+#define LAST_EMBED_REGNUM (96)

 #define NUM_REGS (LAST_EMBED_REGNUM + 1)
 
 #define NUM_REGS (LAST_EMBED_REGNUM + 1)
 

-
+#define FP0_REGNUM 38           /* Floating point register 0 (single float) */
+#define FCRCS_REGNUM 70         /* FP control/status */
+#define FCRIR_REGNUM 71         /* FP implementation/revision */

 #endif
 
 
 #endif
 
 


@@ -366,15 +333,6 @@ struct _sim_cpu {
 #define GPR     (&REGISTERS[0])
 #define GPR_SET(N,VAL) (REGISTERS[(N)] = (VAL))
 
 #define GPR     (&REGISTERS[0])
 #define GPR_SET(N,VAL) (REGISTERS[(N)] = (VAL))
 

-  /* While space is allocated for the floating point registers in the
-     main registers array, they are stored separatly.  This is because
-     their size may not necessarily match the size of either the
-     general-purpose or system specific registers */
-#define NR_FGR  (32)
-#define FGRIDX  (38)
-  fp_word fgr[NR_FGR];
-#define FGR     ((CPU)->fgr)
-

 #define LO      (REGISTERS[33])
 #define HI      (REGISTERS[34])
 #define PCIDX  37
 #define LO      (REGISTERS[33])
 #define HI      (REGISTERS[34])
 #define PCIDX  37


@@ -391,6 +349,51 @@ struct _sim_cpu {
 #define DEPC   (REGISTERS[87])
 #define EPC    (REGISTERS[88])
 
 #define DEPC   (REGISTERS[87])
 #define EPC    (REGISTERS[88])
 

+#define AC0LOIDX       (33)    /* Must be the same register as LO */
+#define AC0HIIDX       (34)    /* Must be the same register as HI */
+#define AC1LOIDX       (90)
+#define AC1HIIDX       (91)
+#define AC2LOIDX       (92)
+#define AC2HIIDX       (93)
+#define AC3LOIDX       (94)
+#define AC3HIIDX       (95)
+
+#define DSPLO(N)       (REGISTERS[DSPLO_REGNUM[N]])
+#define DSPHI(N)       (REGISTERS[DSPHI_REGNUM[N]])
+
+#define DSPCRIDX       (96)    /* DSP control register */
+#define DSPCR          (REGISTERS[DSPCRIDX])
+
+#define DSPCR_POS_SHIFT                (0)
+#define DSPCR_POS_MASK         (0x3f)
+#define DSPCR_POS_SMASK                (DSPCR_POS_MASK << DSPCR_POS_SHIFT)
+
+#define DSPCR_SCOUNT_SHIFT     (7)
+#define DSPCR_SCOUNT_MASK      (0x3f)
+#define DSPCR_SCOUNT_SMASK     (DSPCR_SCOUNT_MASK << DSPCR_SCOUNT_SHIFT)
+
+#define DSPCR_CARRY_SHIFT      (13)
+#define DSPCR_CARRY_MASK       (1)
+#define DSPCR_CARRY_SMASK      (DSPCR_CARRY_MASK << DSPCR_CARRY_SHIFT)
+#define DSPCR_CARRY            (1 << DSPCR_CARRY_SHIFT)
+
+#define DSPCR_EFI_SHIFT                (14)
+#define DSPCR_EFI_MASK         (1)
+#define DSPCR_EFI_SMASK                (DSPCR_EFI_MASK << DSPCR_EFI_SHIFT)
+#define DSPCR_EFI              (1 << DSPCR_EFI_MASK)
+
+#define DSPCR_OUFLAG_SHIFT     (16)
+#define DSPCR_OUFLAG_MASK      (0xff)
+#define DSPCR_OUFLAG_SMASK     (DSPCR_OUFLAG_MASK << DSPCR_OUFLAG_SHIFT)
+#define DSPCR_OUFLAG4          (1 << (DSPCR_OUFLAG_SHIFT + 4))
+#define DSPCR_OUFLAG5          (1 << (DSPCR_OUFLAG_SHIFT + 5))
+#define DSPCR_OUFLAG6          (1 << (DSPCR_OUFLAG_SHIFT + 6))
+#define DSPCR_OUFLAG7          (1 << (DSPCR_OUFLAG_SHIFT + 7))
+
+#define DSPCR_CCOND_SHIFT      (24)
+#define DSPCR_CCOND_MASK       (0xf)
+#define DSPCR_CCOND_SMASK      (DSPCR_CCOND_MASK << DSPCR_CCOND_SHIFT)
+

   /* All internal state modified by signal_exception() that may need to be
      rolled back for passing moment-of-exception image back to gdb. */
   unsigned_word exc_trigger_registers[LAST_EMBED_REGNUM + 1];
   /* All internal state modified by signal_exception() that may need to be
      rolled back for passing moment-of-exception image back to gdb. */
   unsigned_word exc_trigger_registers[LAST_EMBED_REGNUM + 1];


@@ -425,7 +428,16 @@ struct _sim_cpu {
 #define NR_COP0_GPR    32
   unsigned_word cop0_gpr[NR_COP0_GPR];
 #define COP0_GPR       ((CPU)->cop0_gpr)
 #define NR_COP0_GPR    32
   unsigned_word cop0_gpr[NR_COP0_GPR];
 #define COP0_GPR       ((CPU)->cop0_gpr)

-#define COP0_BADVADDR ((unsigned32)(COP0_GPR[8]))
+#define COP0_BADVADDR  (COP0_GPR[8])
+
+  /* While space is allocated for the floating point registers in the
+     main registers array, they are stored separatly.  This is because
+     their size may not necessarily match the size of either the
+     general-purpose or system specific registers.  */
+#define NR_FGR    (32)
+#define FGR_BASE  FP0_REGNUM
+  fp_word fgr[NR_FGR];
+#define FGR       ((CPU)->fgr)

 
   /* Keep the current format state for each register: */
   FP_formats fpr_state[32];
 
   /* Keep the current format state for each register: */
   FP_formats fpr_state[32];


@@ -456,10 +468,6 @@ struct _sim_cpu {
   hilo_history lo_history;
 #define LOHISTORY (&(CPU)->lo_history)
 
   hilo_history lo_history;
 #define LOHISTORY (&(CPU)->lo_history)
 

-#define check_branch_bug() 
-#define mark_branch_bug(TARGET) 
-
-

 
   sim_cpu_base base;
 };
 
   sim_cpu_base base;
 };


@@ -712,12 +720,26 @@ unsigned64 value_fpr (SIM_STATE, int fpr, FP_formats);
 #define ValueFPR(FPR,FMT) value_fpr (SIM_ARGS, (FPR), (FMT))
 void store_fpr (SIM_STATE, int fpr, FP_formats fmt, unsigned64 value);
 #define StoreFPR(FPR,FMT,VALUE) store_fpr (SIM_ARGS, (FPR), (FMT), (VALUE))
 #define ValueFPR(FPR,FMT) value_fpr (SIM_ARGS, (FPR), (FMT))
 void store_fpr (SIM_STATE, int fpr, FP_formats fmt, unsigned64 value);
 #define StoreFPR(FPR,FMT,VALUE) store_fpr (SIM_ARGS, (FPR), (FMT), (VALUE))

+unsigned64 ps_lower (SIM_STATE, unsigned64 op);
+#define PSLower(op) ps_lower (SIM_ARGS, op)
+unsigned64 ps_upper (SIM_STATE, unsigned64 op);
+#define PSUpper(op) ps_upper (SIM_ARGS, op)
+unsigned64 pack_ps (SIM_STATE, unsigned64 op1, unsigned64 op2, FP_formats from);
+#define PackPS(op1,op2) pack_ps (SIM_ARGS, op1, op2, fmt_single)
+
+
+/* FCR access.  */
+unsigned_word value_fcr (SIM_STATE, int fcr);
+#define ValueFCR(FCR) value_fcr (SIM_ARGS, (FCR))
+void store_fcr (SIM_STATE, int fcr, unsigned_word value);
+#define StoreFCR(FCR,VALUE) store_fcr (SIM_ARGS, (FCR), (VALUE))
+void test_fcsr (SIM_STATE);
+#define TestFCSR() test_fcsr (SIM_ARGS)

 
 
 /* FPU operations.  */
 
 
 /* FPU operations.  */

-int NaN (unsigned64 op, FP_formats fmt);
-int Less (unsigned64 op1, unsigned64 op2, FP_formats fmt);
-int Equal (unsigned64 op1, unsigned64 op2, FP_formats fmt);
+void fp_cmp (SIM_STATE, unsigned64 op1, unsigned64 op2, FP_formats fmt, int abs, int cond, int cc);
+#define Compare(op1,op2,fmt,cond,cc) fp_cmp(SIM_ARGS, op1, op2, fmt, 0, cond, cc)

 unsigned64 fp_abs (SIM_STATE, unsigned64 op, FP_formats fmt);
 #define AbsoluteValue(op,fmt) fp_abs(SIM_ARGS, op, fmt)
 unsigned64 fp_neg (SIM_STATE, unsigned64 op, FP_formats fmt);
 unsigned64 fp_abs (SIM_STATE, unsigned64 op, FP_formats fmt);
 #define AbsoluteValue(op,fmt) fp_abs(SIM_ARGS, op, fmt)
 unsigned64 fp_neg (SIM_STATE, unsigned64 op, FP_formats fmt);


@@ -734,8 +756,42 @@ unsigned64 fp_recip (SIM_STATE, unsigned64 op, FP_formats fmt);
 #define Recip(op,fmt) fp_recip(SIM_ARGS, op, fmt)
 unsigned64 fp_sqrt (SIM_STATE, unsigned64 op, FP_formats fmt);
 #define SquareRoot(op,fmt) fp_sqrt(SIM_ARGS, op, fmt)
 #define Recip(op,fmt) fp_recip(SIM_ARGS, op, fmt)
 unsigned64 fp_sqrt (SIM_STATE, unsigned64 op, FP_formats fmt);
 #define SquareRoot(op,fmt) fp_sqrt(SIM_ARGS, op, fmt)

+unsigned64 fp_rsqrt (SIM_STATE, unsigned64 op, FP_formats fmt);
+#define RSquareRoot(op,fmt) fp_rsqrt(SIM_ARGS, op, fmt)
+unsigned64 fp_madd (SIM_STATE, unsigned64 op1, unsigned64 op2,
+                   unsigned64 op3, FP_formats fmt);
+#define MultiplyAdd(op1,op2,op3,fmt) fp_madd(SIM_ARGS, op1, op2, op3, fmt)
+unsigned64 fp_msub (SIM_STATE, unsigned64 op1, unsigned64 op2,
+                   unsigned64 op3, FP_formats fmt);
+#define MultiplySub(op1,op2,op3,fmt) fp_msub(SIM_ARGS, op1, op2, op3, fmt)
+unsigned64 fp_nmadd (SIM_STATE, unsigned64 op1, unsigned64 op2,
+                    unsigned64 op3, FP_formats fmt);
+#define NegMultiplyAdd(op1,op2,op3,fmt) fp_nmadd(SIM_ARGS, op1, op2, op3, fmt)
+unsigned64 fp_nmsub (SIM_STATE, unsigned64 op1, unsigned64 op2,
+                    unsigned64 op3, FP_formats fmt);
+#define NegMultiplySub(op1,op2,op3,fmt) fp_nmsub(SIM_ARGS, op1, op2, op3, fmt)

 unsigned64 convert (SIM_STATE, int rm, unsigned64 op, FP_formats from, FP_formats to);
 #define Convert(rm,op,from,to) convert (SIM_ARGS, rm, op, from, to)
 unsigned64 convert (SIM_STATE, int rm, unsigned64 op, FP_formats from, FP_formats to);
 #define Convert(rm,op,from,to) convert (SIM_ARGS, rm, op, from, to)

+unsigned64 convert_ps (SIM_STATE, int rm, unsigned64 op, FP_formats from,
+                      FP_formats to);
+#define ConvertPS(rm,op,from,to) convert_ps (SIM_ARGS, rm, op, from, to)
+
+
+/* MIPS-3D ASE operations.  */
+#define CompareAbs(op1,op2,fmt,cond,cc) \
+fp_cmp(SIM_ARGS, op1, op2, fmt, 1, cond, cc)
+unsigned64 fp_add_r (SIM_STATE, unsigned64 op1, unsigned64 op2, FP_formats fmt);
+#define AddR(op1,op2,fmt) fp_add_r(SIM_ARGS, op1, op2, fmt)
+unsigned64 fp_mul_r (SIM_STATE, unsigned64 op1, unsigned64 op2, FP_formats fmt);
+#define MultiplyR(op1,op2,fmt) fp_mul_r(SIM_ARGS, op1, op2, fmt)
+unsigned64 fp_recip1 (SIM_STATE, unsigned64 op, FP_formats fmt);
+#define Recip1(op,fmt) fp_recip1(SIM_ARGS, op, fmt)
+unsigned64 fp_recip2 (SIM_STATE, unsigned64 op1, unsigned64 op2, FP_formats fmt);
+#define Recip2(op1,op2,fmt) fp_recip2(SIM_ARGS, op1, op2, fmt)
+unsigned64 fp_rsqrt1 (SIM_STATE, unsigned64 op, FP_formats fmt);
+#define RSquareRoot1(op,fmt) fp_rsqrt1(SIM_ARGS, op, fmt)
+unsigned64 fp_rsqrt2 (SIM_STATE, unsigned64 op1, unsigned64 op2, FP_formats fmt);
+#define RSquareRoot2(op1,op2,fmt) fp_rsqrt2(SIM_ARGS, op1, op2, fmt)

 
 
 /* MDMX access.  */
 
 
 /* MDMX access.  */


@@ -922,6 +978,9 @@ INLINE_SIM_MAIN (unsigned16) ifetch16 PARAMS ((SIM_DESC sd, sim_cpu *cpu, addres
 void dotrace PARAMS ((SIM_DESC sd, sim_cpu *cpu, FILE *tracefh, int type, SIM_ADDR address, int width, char *comment, ...));
 extern FILE *tracefh;
 
 void dotrace PARAMS ((SIM_DESC sd, sim_cpu *cpu, FILE *tracefh, int type, SIM_ADDR address, int width, char *comment, ...));
 extern FILE *tracefh;
 

+extern int DSPLO_REGNUM[4];
+extern int DSPHI_REGNUM[4];
+

 INLINE_SIM_MAIN (void) pending_tick PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia));
 extern SIM_CORE_SIGNAL_FN mips_core_signal;
 
 INLINE_SIM_MAIN (void) pending_tick PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia));
 extern SIM_CORE_SIGNAL_FN mips_core_signal;
 


@@ -935,6 +994,24 @@ void mips_cpu_exception_trigger(SIM_DESC sd, sim_cpu* cpu, address_word pc);
 void mips_cpu_exception_suspend(SIM_DESC sd, sim_cpu* cpu, int exception);
 void mips_cpu_exception_resume(SIM_DESC sd, sim_cpu* cpu, int exception);
 
 void mips_cpu_exception_suspend(SIM_DESC sd, sim_cpu* cpu, int exception);
 void mips_cpu_exception_resume(SIM_DESC sd, sim_cpu* cpu, int exception);
 

+#ifdef MIPS_MACH_MULTI
+extern int mips_mach_multi(SIM_DESC sd);
+#define MIPS_MACH(SD)  mips_mach_multi(SD)
+#else
+#define        MIPS_MACH(SD)   MIPS_MACH_DEFAULT
+#endif
+
+/* Macros for determining whether a MIPS IV or MIPS V part is subject
+   to the hi/lo restrictions described in mips.igen.  */
+
+#define MIPS_MACH_HAS_MT_HILO_HAZARD(SD) \
+  (MIPS_MACH (SD) != bfd_mach_mips5500)
+
+#define MIPS_MACH_HAS_MULT_HILO_HAZARD(SD) \
+  (MIPS_MACH (SD) != bfd_mach_mips5500)
+
+#define MIPS_MACH_HAS_DIV_HILO_HAZARD(SD) \
+  (MIPS_MACH (SD) != bfd_mach_mips5500)

 
 #if H_REVEALS_MODULE_P (SIM_MAIN_INLINE)
 #include "sim-main.c"
 
 #if H_REVEALS_MODULE_P (SIM_MAIN_INLINE)
 #include "sim-main.c"