* common/aclocal.m4: Pass ../../intl to ZW_GNU_GETTEXT_SISTER_DIR.

[deliverable/binutils-gdb.git] / sim / mips / sim-main.h

diff --git a/sim/mips/sim-main.h b/sim/mips/sim-main.h
index 833fd5f9b01b33ad355db93f1b9d284ffc725e9a..76e6374e01dcc7962683b7f4ad73af66e51e83d1 100644 (file)
--- a/sim/mips/sim-main.h
+++ b/sim/mips/sim-main.h
@@ -1,5 +1,5 @@
 /* MIPS Simulator definition.
 /* MIPS Simulator definition.

-   Copyright (C) 1997, 1998 Free Software Foundation, Inc.
+   Copyright (C) 1997, 1998, 2003 Free Software Foundation, Inc.

    Contributed by Cygnus Support.
 
 This file is part of GDB, the GNU debugger.
    Contributed by Cygnus Support.
 
 This file is part of GDB, the GNU debugger.


@@ -41,7 +41,7 @@ mips_core_signal ((SD), (CPU), (CIA), (MAP), (NR_BYTES), (ADDR), (TRANSFER), (ER
 typedef address_word sim_cia;
 
 #include "sim-base.h"
 typedef address_word sim_cia;
 
 #include "sim-base.h"

-
+#include "bfd.h"

 
 /* Deprecated macros and types for manipulating 64bit values.  Use
    ../common/sim-bits.h and ../common/sim-endian.h macros instead. */
 
 /* Deprecated macros and types for manipulating 64bit values.  Use
    ../common/sim-bits.h and ../common/sim-endian.h macros instead. */


@@ -82,6 +82,10 @@ typedef enum {
  fmt_uninterpreted_64 = 0x80000000U,
 } FP_formats;
 
  fmt_uninterpreted_64 = 0x80000000U,
 } FP_formats;
 

+/* For paired word (pw) operations, the opcode representation is fmt_word,
+   but register transfers (StoreFPR, ValueFPR, etc.) are done as fmt_long.  */
+#define fmt_pw fmt_long
+

 /* This should be the COC1 value at the start of the preceding
    instruction: */
 #define PREVCOC1() ((STATE & simPCOC1) ? 1 : 0)
 /* This should be the COC1 value at the start of the preceding
    instruction: */
 #define PREVCOC1() ((STATE & simPCOC1) ? 1 : 0)


@@ -308,7 +312,7 @@ struct _sim_cpu {
    state. */
 
 #ifndef TM_MIPS_H
    state. */
 
 #ifndef TM_MIPS_H

-#define LAST_EMBED_REGNUM (89)
+#define LAST_EMBED_REGNUM (96)

 #define NUM_REGS (LAST_EMBED_REGNUM + 1)
 
 #define FP0_REGNUM 38           /* Floating point register 0 (single float) */
 #define NUM_REGS (LAST_EMBED_REGNUM + 1)
 
 #define FP0_REGNUM 38           /* Floating point register 0 (single float) */


@@ -345,6 +349,51 @@ struct _sim_cpu {
 #define DEPC   (REGISTERS[87])
 #define EPC    (REGISTERS[88])
 
 #define DEPC   (REGISTERS[87])
 #define EPC    (REGISTERS[88])
 

+#define AC0LOIDX       (33)    /* Must be the same register as LO */
+#define AC0HIIDX       (34)    /* Must be the same register as HI */
+#define AC1LOIDX       (90)
+#define AC1HIIDX       (91)
+#define AC2LOIDX       (92)
+#define AC2HIIDX       (93)
+#define AC3LOIDX       (94)
+#define AC3HIIDX       (95)
+
+#define DSPLO(N)       (REGISTERS[DSPLO_REGNUM[N]])
+#define DSPHI(N)       (REGISTERS[DSPHI_REGNUM[N]])
+
+#define DSPCRIDX       (96)    /* DSP control register */
+#define DSPCR          (REGISTERS[DSPCRIDX])
+
+#define DSPCR_POS_SHIFT                (0)
+#define DSPCR_POS_MASK         (0x3f)
+#define DSPCR_POS_SMASK                (DSPCR_POS_MASK << DSPCR_POS_SHIFT)
+
+#define DSPCR_SCOUNT_SHIFT     (7)
+#define DSPCR_SCOUNT_MASK      (0x3f)
+#define DSPCR_SCOUNT_SMASK     (DSPCR_SCOUNT_MASK << DSPCR_SCOUNT_SHIFT)
+
+#define DSPCR_CARRY_SHIFT      (13)
+#define DSPCR_CARRY_MASK       (1)
+#define DSPCR_CARRY_SMASK      (DSPCR_CARRY_MASK << DSPCR_CARRY_SHIFT)
+#define DSPCR_CARRY            (1 << DSPCR_CARRY_SHIFT)
+
+#define DSPCR_EFI_SHIFT                (14)
+#define DSPCR_EFI_MASK         (1)
+#define DSPCR_EFI_SMASK                (DSPCR_EFI_MASK << DSPCR_EFI_SHIFT)
+#define DSPCR_EFI              (1 << DSPCR_EFI_MASK)
+
+#define DSPCR_OUFLAG_SHIFT     (16)
+#define DSPCR_OUFLAG_MASK      (0xff)
+#define DSPCR_OUFLAG_SMASK     (DSPCR_OUFLAG_MASK << DSPCR_OUFLAG_SHIFT)
+#define DSPCR_OUFLAG4          (1 << (DSPCR_OUFLAG_SHIFT + 4))
+#define DSPCR_OUFLAG5          (1 << (DSPCR_OUFLAG_SHIFT + 5))
+#define DSPCR_OUFLAG6          (1 << (DSPCR_OUFLAG_SHIFT + 6))
+#define DSPCR_OUFLAG7          (1 << (DSPCR_OUFLAG_SHIFT + 7))
+
+#define DSPCR_CCOND_SHIFT      (24)
+#define DSPCR_CCOND_MASK       (0xf)
+#define DSPCR_CCOND_SMASK      (DSPCR_CCOND_MASK << DSPCR_CCOND_SHIFT)
+

   /* All internal state modified by signal_exception() that may need to be
      rolled back for passing moment-of-exception image back to gdb. */
   unsigned_word exc_trigger_registers[LAST_EMBED_REGNUM + 1];
   /* All internal state modified by signal_exception() that may need to be
      rolled back for passing moment-of-exception image back to gdb. */
   unsigned_word exc_trigger_registers[LAST_EMBED_REGNUM + 1];


@@ -379,7 +428,7 @@ struct _sim_cpu {
 #define NR_COP0_GPR    32
   unsigned_word cop0_gpr[NR_COP0_GPR];
 #define COP0_GPR       ((CPU)->cop0_gpr)
 #define NR_COP0_GPR    32
   unsigned_word cop0_gpr[NR_COP0_GPR];
 #define COP0_GPR       ((CPU)->cop0_gpr)

-#define COP0_BADVADDR ((unsigned32)(COP0_GPR[8]))
+#define COP0_BADVADDR  (COP0_GPR[8])

 
   /* While space is allocated for the floating point registers in the
      main registers array, they are stored separatly.  This is because
 
   /* While space is allocated for the floating point registers in the
      main registers array, they are stored separatly.  This is because


@@ -419,10 +468,6 @@ struct _sim_cpu {
   hilo_history lo_history;
 #define LOHISTORY (&(CPU)->lo_history)
 
   hilo_history lo_history;
 #define LOHISTORY (&(CPU)->lo_history)
 

-#define check_branch_bug() 
-#define mark_branch_bug(TARGET) 
-
-

 
   sim_cpu_base base;
 };
 
   sim_cpu_base base;
 };


@@ -732,6 +777,23 @@ unsigned64 convert_ps (SIM_STATE, int rm, unsigned64 op, FP_formats from,
 #define ConvertPS(rm,op,from,to) convert_ps (SIM_ARGS, rm, op, from, to)
 
 
 #define ConvertPS(rm,op,from,to) convert_ps (SIM_ARGS, rm, op, from, to)
 
 

+/* MIPS-3D ASE operations.  */
+#define CompareAbs(op1,op2,fmt,cond,cc) \
+fp_cmp(SIM_ARGS, op1, op2, fmt, 1, cond, cc)
+unsigned64 fp_add_r (SIM_STATE, unsigned64 op1, unsigned64 op2, FP_formats fmt);
+#define AddR(op1,op2,fmt) fp_add_r(SIM_ARGS, op1, op2, fmt)
+unsigned64 fp_mul_r (SIM_STATE, unsigned64 op1, unsigned64 op2, FP_formats fmt);
+#define MultiplyR(op1,op2,fmt) fp_mul_r(SIM_ARGS, op1, op2, fmt)
+unsigned64 fp_recip1 (SIM_STATE, unsigned64 op, FP_formats fmt);
+#define Recip1(op,fmt) fp_recip1(SIM_ARGS, op, fmt)
+unsigned64 fp_recip2 (SIM_STATE, unsigned64 op1, unsigned64 op2, FP_formats fmt);
+#define Recip2(op1,op2,fmt) fp_recip2(SIM_ARGS, op1, op2, fmt)
+unsigned64 fp_rsqrt1 (SIM_STATE, unsigned64 op, FP_formats fmt);
+#define RSquareRoot1(op,fmt) fp_rsqrt1(SIM_ARGS, op, fmt)
+unsigned64 fp_rsqrt2 (SIM_STATE, unsigned64 op1, unsigned64 op2, FP_formats fmt);
+#define RSquareRoot2(op1,op2,fmt) fp_rsqrt2(SIM_ARGS, op1, op2, fmt)
+
+

 /* MDMX access.  */
 
 typedef unsigned int MX_fmtsel;   /* MDMX format select field (5 bits).  */
 /* MDMX access.  */
 
 typedef unsigned int MX_fmtsel;   /* MDMX format select field (5 bits).  */


@@ -916,6 +978,9 @@ INLINE_SIM_MAIN (unsigned16) ifetch16 PARAMS ((SIM_DESC sd, sim_cpu *cpu, addres
 void dotrace PARAMS ((SIM_DESC sd, sim_cpu *cpu, FILE *tracefh, int type, SIM_ADDR address, int width, char *comment, ...));
 extern FILE *tracefh;
 
 void dotrace PARAMS ((SIM_DESC sd, sim_cpu *cpu, FILE *tracefh, int type, SIM_ADDR address, int width, char *comment, ...));
 extern FILE *tracefh;
 

+extern int DSPLO_REGNUM[4];
+extern int DSPHI_REGNUM[4];
+

 INLINE_SIM_MAIN (void) pending_tick PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia));
 extern SIM_CORE_SIGNAL_FN mips_core_signal;
 
 INLINE_SIM_MAIN (void) pending_tick PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia));
 extern SIM_CORE_SIGNAL_FN mips_core_signal;
 


@@ -929,6 +994,24 @@ void mips_cpu_exception_trigger(SIM_DESC sd, sim_cpu* cpu, address_word pc);
 void mips_cpu_exception_suspend(SIM_DESC sd, sim_cpu* cpu, int exception);
 void mips_cpu_exception_resume(SIM_DESC sd, sim_cpu* cpu, int exception);
 
 void mips_cpu_exception_suspend(SIM_DESC sd, sim_cpu* cpu, int exception);
 void mips_cpu_exception_resume(SIM_DESC sd, sim_cpu* cpu, int exception);
 

+#ifdef MIPS_MACH_MULTI
+extern int mips_mach_multi(SIM_DESC sd);
+#define MIPS_MACH(SD)  mips_mach_multi(SD)
+#else
+#define        MIPS_MACH(SD)   MIPS_MACH_DEFAULT
+#endif
+
+/* Macros for determining whether a MIPS IV or MIPS V part is subject
+   to the hi/lo restrictions described in mips.igen.  */
+
+#define MIPS_MACH_HAS_MT_HILO_HAZARD(SD) \
+  (MIPS_MACH (SD) != bfd_mach_mips5500)
+
+#define MIPS_MACH_HAS_MULT_HILO_HAZARD(SD) \
+  (MIPS_MACH (SD) != bfd_mach_mips5500)
+
+#define MIPS_MACH_HAS_DIV_HILO_HAZARD(SD) \
+  (MIPS_MACH (SD) != bfd_mach_mips5500)

 
 #if H_REVEALS_MODULE_P (SIM_MAIN_INLINE)
 #include "sim-main.c"
 
 #if H_REVEALS_MODULE_P (SIM_MAIN_INLINE)
 #include "sim-main.c"