+#define ACX (REGISTERS[89])
+
+#define AC0LOIDX (33) /* Must be the same register as LO */
+#define AC0HIIDX (34) /* Must be the same register as HI */
+#define AC1LOIDX (90)
+#define AC1HIIDX (91)
+#define AC2LOIDX (92)
+#define AC2HIIDX (93)
+#define AC3LOIDX (94)
+#define AC3HIIDX (95)
+
+#define DSPLO(N) (REGISTERS[DSPLO_REGNUM[N]])
+#define DSPHI(N) (REGISTERS[DSPHI_REGNUM[N]])
+
+#define DSPCRIDX (96) /* DSP control register */
+#define DSPCR (REGISTERS[DSPCRIDX])
+
+#define DSPCR_POS_SHIFT (0)
+#define DSPCR_POS_MASK (0x3f)
+#define DSPCR_POS_SMASK (DSPCR_POS_MASK << DSPCR_POS_SHIFT)
+
+#define DSPCR_SCOUNT_SHIFT (7)
+#define DSPCR_SCOUNT_MASK (0x3f)
+#define DSPCR_SCOUNT_SMASK (DSPCR_SCOUNT_MASK << DSPCR_SCOUNT_SHIFT)
+
+#define DSPCR_CARRY_SHIFT (13)
+#define DSPCR_CARRY_MASK (1)
+#define DSPCR_CARRY_SMASK (DSPCR_CARRY_MASK << DSPCR_CARRY_SHIFT)
+#define DSPCR_CARRY (1 << DSPCR_CARRY_SHIFT)
+
+#define DSPCR_EFI_SHIFT (14)
+#define DSPCR_EFI_MASK (1)
+#define DSPCR_EFI_SMASK (DSPCR_EFI_MASK << DSPCR_EFI_SHIFT)
+#define DSPCR_EFI (1 << DSPCR_EFI_MASK)
+
+#define DSPCR_OUFLAG_SHIFT (16)
+#define DSPCR_OUFLAG_MASK (0xff)
+#define DSPCR_OUFLAG_SMASK (DSPCR_OUFLAG_MASK << DSPCR_OUFLAG_SHIFT)
+#define DSPCR_OUFLAG4 (1 << (DSPCR_OUFLAG_SHIFT + 4))
+#define DSPCR_OUFLAG5 (1 << (DSPCR_OUFLAG_SHIFT + 5))
+#define DSPCR_OUFLAG6 (1 << (DSPCR_OUFLAG_SHIFT + 6))
+#define DSPCR_OUFLAG7 (1 << (DSPCR_OUFLAG_SHIFT + 7))
+
+#define DSPCR_CCOND_SHIFT (24)
+#define DSPCR_CCOND_MASK (0xf)
+#define DSPCR_CCOND_SMASK (DSPCR_CCOND_MASK << DSPCR_CCOND_SHIFT)