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Automatic date update in version.in
[deliverable/binutils-gdb.git]
/
sim
/
mn10300
/
am33.igen
diff --git
a/sim/mn10300/am33.igen
b/sim/mn10300/am33.igen
index b5d0a850d2593d528d0337284b321a8dccb26dc0..5bc96aca6164efb19c08a24cc3870d144350a959 100644
(file)
--- a/
sim/mn10300/am33.igen
+++ b/
sim/mn10300/am33.igen
@@
-34,7
+34,7
@@
case 4:
return REG_MCVF;
default:
case 4:
return REG_MCVF;
default:
-
abort (
);
+
sim_engine_abort (SD, CPU, cia, "%s:%d: bad switch\n", __FILE__, __LINE__
);
}
}
}
}
@@
-42,6
+42,7
@@
8.0xf0+4.0x2,00,2.AN0:D0m:::mov
"mov"
*am33
8.0xf0+4.0x2,00,2.AN0:D0m:::mov
"mov"
*am33
+*am33_2
{
PC = cia;
State.regs[REG_A0 + AN0] = State.regs[REG_USP];
{
PC = cia;
State.regs[REG_A0 + AN0] = State.regs[REG_USP];
@@
-52,6
+53,7
@@
8.0xf0+4.0x2,01,2.AN0:D0n:::mov
"mov"
*am33
8.0xf0+4.0x2,01,2.AN0:D0n:::mov
"mov"
*am33
+*am33_2
{
PC = cia;
State.regs[REG_A0 + AN0] = State.regs[REG_SSP];
{
PC = cia;
State.regs[REG_A0 + AN0] = State.regs[REG_SSP];
@@
-62,6
+64,7
@@
8.0xf0+4.0x2,10,2.AN0:D0o:::mov
"mov"
*am33
8.0xf0+4.0x2,10,2.AN0:D0o:::mov
"mov"
*am33
+*am33_2
{
PC = cia;
State.regs[REG_A0 + AN0] = State.regs[REG_MSP];
{
PC = cia;
State.regs[REG_A0 + AN0] = State.regs[REG_MSP];
@@
-72,6
+75,7
@@
8.0xf0+4.0x2,11,2.AN0:D0p:::mov
"mov"
*am33
8.0xf0+4.0x2,11,2.AN0:D0p:::mov
"mov"
*am33
+*am33_2
{
PC = cia;
State.regs[REG_A0 + AN0] = PC;
{
PC = cia;
State.regs[REG_A0 + AN0] = PC;
@@
-82,6
+86,7
@@
8.0xf0+4.0x3,2.AM1,00:D0q:::mov
"mov"
*am33
8.0xf0+4.0x3,2.AM1,00:D0q:::mov
"mov"
*am33
+*am33_2
{
PC = cia;
State.regs[REG_USP] = State.regs[REG_A0 + AM1];
{
PC = cia;
State.regs[REG_USP] = State.regs[REG_A0 + AM1];
@@
-91,6
+96,7
@@
8.0xf0+4.0x3,2.AM1,01:D0r:::mov
"mov"
*am33
8.0xf0+4.0x3,2.AM1,01:D0r:::mov
"mov"
*am33
+*am33_2
{
PC = cia;
State.regs[REG_SSP] = State.regs[REG_A0 + AM1];
{
PC = cia;
State.regs[REG_SSP] = State.regs[REG_A0 + AM1];
@@
-100,6
+106,7
@@
8.0xf0+4.0x3,2.AM1,10:D0s:::mov
"mov"
*am33
8.0xf0+4.0x3,2.AM1,10:D0s:::mov
"mov"
*am33
+*am33_2
{
PC = cia;
State.regs[REG_MSP] = State.regs[REG_A0 + AM1];
{
PC = cia;
State.regs[REG_MSP] = State.regs[REG_A0 + AM1];
@@
-110,6
+117,7
@@
8.0xf0+4.0xe,IMM4:D0t:::syscall
"syscall"
*am33
8.0xf0+4.0xe,IMM4:D0t:::syscall
"syscall"
*am33
+*am33_2
{
unsigned32 sp, next_pc;
{
unsigned32 sp, next_pc;
@@
-127,6
+135,7
@@
8.0xf2+4.0xe,11,2.DN0:D0u:::mov
"mov"
*am33
8.0xf2+4.0xe,11,2.DN0:D0u:::mov
"mov"
*am33
+*am33_2
{
PC = cia;
State.regs[REG_D0 + DN0] = PSW;
{
PC = cia;
State.regs[REG_D0 + DN0] = PSW;
@@
-137,6
+146,7
@@
8.0xf2+4.0xf,2.DM1,01:D0v:::mov
"mov"
*am33
8.0xf2+4.0xf,2.DM1,01:D0v:::mov
"mov"
*am33
+*am33_2
{
PC = cia;
PSW = State.regs[REG_D0 + DM1];
{
PC = cia;
PSW = State.regs[REG_D0 + DM1];
@@
-146,6
+156,7
@@
8.0xf5+00,2.AM1,4.RN0:D0w:::mov
"mov"
*am33
8.0xf5+00,2.AM1,4.RN0:D0w:::mov
"mov"
*am33
+*am33_2
{
int destreg = translate_rreg (SD_, RN0);
{
int destreg = translate_rreg (SD_, RN0);
@@
-157,6
+168,7
@@
8.0xf5+01,2.DM1,4.RN0:D0x:::mov
"mov"
*am33
8.0xf5+01,2.DM1,4.RN0:D0x:::mov
"mov"
*am33
+*am33_2
{
int destreg = translate_rreg (SD_, RN0);
{
int destreg = translate_rreg (SD_, RN0);
@@
-168,6
+180,7
@@
8.0xf5+10,4.RM1,2.AN0:D0y:::mov
"mov"
*am33
8.0xf5+10,4.RM1,2.AN0:D0y:::mov
"mov"
*am33
+*am33_2
{
int destreg = translate_rreg (SD_, RM1);
{
int destreg = translate_rreg (SD_, RM1);
@@
-179,6
+192,7
@@
8.0xf5+11,4.RM1,2.DN0:D0z:::mov
"mov"
*am33
8.0xf5+11,4.RM1,2.DN0:D0z:::mov
"mov"
*am33
+*am33_2
{
int destreg = translate_rreg (SD_, RM1);
{
int destreg = translate_rreg (SD_, RM1);
@@
-191,6
+205,7
@@
8.0xf8+8.0xce+8.REGS:D1a:::movm
"movm"
*am33
8.0xf8+8.0xce+8.REGS:D1a:::movm
"movm"
*am33
+*am33_2
{
unsigned32 usp = State.regs[REG_USP];
unsigned32 mask;
{
unsigned32 usp = State.regs[REG_USP];
unsigned32 mask;
@@
-242,6
+257,7
@@
}
if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33
}
if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33
+ || STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33_2
)
{
if (mask & 0x1)
)
{
if (mask & 0x1)
@@
-283,11
+299,16
@@
8.0xf8+8.0xcf+8.REGS:D1b:::movm
"movm"
*am33
8.0xf8+8.0xcf+8.REGS:D1b:::movm
"movm"
*am33
+*am33_2
{
unsigned32 usp = State.regs[REG_USP];
unsigned32 mask;
{
unsigned32 usp = State.regs[REG_USP];
unsigned32 mask;
+ PC = cia;
+ mask = REGS;
+
if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33
if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33
+ || STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33_2
)
{
if (mask & 0x4)
)
{
if (mask & 0x4)
@@
-372,6
+393,7
@@
8.0xfc+8.0xfc+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:4a:::and
"and"
*am33
8.0xfc+8.0xfc+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:4a:::and
"and"
*am33
+*am33_2
{
PC = cia;
PSW &= FETCH32(IMM32A, IMM32B, IMM32C, IMM32D);
{
PC = cia;
PSW &= FETCH32(IMM32A, IMM32B, IMM32C, IMM32D);
@@
-381,6
+403,7
@@
8.0xfc+8.0xfd+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4a:::or
"or"
*am33
8.0xfc+8.0xfd+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4a:::or
"or"
*am33
+*am33_2
{
PC = cia;
PSW |= FETCH32(IMM32A, IMM32B, IMM32C, IMM32D);
{
PC = cia;
PSW |= FETCH32(IMM32A, IMM32B, IMM32C, IMM32D);
@@
-390,6
+413,7
@@
8.0xf9+8.0x08+4.RM2,4.RN0!RM2:D1g:::mov
"mov"
*am33
8.0xf9+8.0x08+4.RM2,4.RN0!RM2:D1g:::mov
"mov"
*am33
+*am33_2
{
int srcreg, dstreg;
{
int srcreg, dstreg;
@@
-404,6
+428,7
@@
8.0xf9+8.0x18+4.RN0,4.RN2=RN0:D1:::ext
"mov"
*am33
8.0xf9+8.0x18+4.RN0,4.RN2=RN0:D1:::ext
"mov"
*am33
+*am33_2
{
int srcreg;
{
int srcreg;
@@
-419,6
+444,7
@@
8.0xf9+8.0x28+4.RM2,4.RN0!RM2:D1:::extb
"extb"
*am33
8.0xf9+8.0x28+4.RM2,4.RN0!RM2:D1:::extb
"extb"
*am33
+*am33_2
{
int srcreg, dstreg;
{
int srcreg, dstreg;
@@
-432,6
+458,7
@@
8.0xf9+8.0x38+4.RM2,4.RN0!RM2:D1:::extbu
"extbu"
*am33
8.0xf9+8.0x38+4.RM2,4.RN0!RM2:D1:::extbu
"extbu"
*am33
+*am33_2
{
int srcreg, dstreg;
{
int srcreg, dstreg;
@@
-445,6
+472,7
@@
8.0xf9+8.0x48+4.RM2,4.RN0!RM2:D1:::exth
"exth"
*am33
8.0xf9+8.0x48+4.RM2,4.RN0!RM2:D1:::exth
"exth"
*am33
+*am33_2
{
int srcreg, dstreg;
{
int srcreg, dstreg;
@@
-458,6
+486,7
@@
8.0xf9+8.0x58+4.RM2,4.RN0!RM2:D1:::exthu
"exthu"
*am33
8.0xf9+8.0x58+4.RM2,4.RN0!RM2:D1:::exthu
"exthu"
*am33
+*am33_2
{
int srcreg, dstreg;
{
int srcreg, dstreg;
@@
-471,6
+500,7
@@
8.0xf9+8.0x68+4.RM2,4.RN0=RM2:D1:::clr
"clr"
*am33
8.0xf9+8.0x68+4.RM2,4.RN0=RM2:D1:::clr
"clr"
*am33
+*am33_2
{
int dstreg;
{
int dstreg;
@@
-485,6
+515,7
@@
8.0xf9+8.0x78+4.RM2,4.RN0:D1b:::add
"add"
*am33
8.0xf9+8.0x78+4.RM2,4.RN0:D1b:::add
"add"
*am33
+*am33_2
{
int srcreg, dstreg;
{
int srcreg, dstreg;
@@
-498,6
+529,7
@@
8.0xf9+8.0x88+4.RM2,4.RN0:D1b:::addc
"addc"
*am33
8.0xf9+8.0x88+4.RM2,4.RN0:D1b:::addc
"addc"
*am33
+*am33_2
{
int srcreg, dstreg;
int z, c, n, v;
{
int srcreg, dstreg;
int z, c, n, v;
@@
-527,6
+559,7
@@
8.0xf9+8.0x98+4.RM2,4.RN0:D1b:::sub
"sub"
*am33
8.0xf9+8.0x98+4.RM2,4.RN0:D1b:::sub
"sub"
*am33
+*am33_2
{
int srcreg, dstreg;
{
int srcreg, dstreg;
@@
-540,6
+573,7
@@
8.0xf9+8.0xa8+4.RM2,4.RN0:D1b:::subc
"subc"
*am33
8.0xf9+8.0xa8+4.RM2,4.RN0:D1b:::subc
"subc"
*am33
+*am33_2
{
int srcreg, dstreg;
int z, c, n, v;
{
int srcreg, dstreg;
int z, c, n, v;
@@
-569,6
+603,7
@@
8.0xf9+8.0xb8+4.RN0,4.RN2=RN0:D1:::inc
"inc"
*am33
8.0xf9+8.0xb8+4.RN0,4.RN2=RN0:D1:::inc
"inc"
*am33
+*am33_2
{
int dstreg;
{
int dstreg;
@@
-581,6
+616,7
@@
8.0xf9+8.0xc8+4.RN0,4.RN2=RN0:D1:::inc4
"inc4"
*am33
8.0xf9+8.0xc8+4.RN0,4.RN2=RN0:D1:::inc4
"inc4"
*am33
+*am33_2
{
int dstreg;
{
int dstreg;
@@
-593,6
+629,7
@@
8.0xf9+8.0xd8+4.RM2,4.RN0:D1:::cmp
"cmp"
*am33
8.0xf9+8.0xd8+4.RM2,4.RN0:D1:::cmp
"cmp"
*am33
+*am33_2
{
int srcreg1, srcreg2;
{
int srcreg1, srcreg2;
@@
-606,6
+643,7
@@
8.0xf9+8.0xe8+4.XRM2,4.RN0:D1l:::mov
"mov"
*am33
8.0xf9+8.0xe8+4.XRM2,4.RN0:D1l:::mov
"mov"
*am33
+*am33_2
{
int dstreg, srcreg;
{
int dstreg, srcreg;
@@
-620,6
+658,7
@@
8.0xf9+8.0xf8+4.RM2,4.XRN0:D1m:::mov
"mov"
*am33
8.0xf9+8.0xf8+4.RM2,4.XRN0:D1m:::mov
"mov"
*am33
+*am33_2
{
int srcreg, dstreg;
{
int srcreg, dstreg;
@@
-634,6
+673,7
@@
8.0xf9+8.0x09+4.RM2,4.RN0:D1a:::and
"and"
*am33
8.0xf9+8.0x09+4.RM2,4.RN0:D1a:::and
"and"
*am33
+*am33_2
{
int srcreg, dstreg;
int z, n;
{
int srcreg, dstreg;
int z, n;
@@
-654,6
+694,7
@@
8.0xf9+8.0x19+4.RM2,4.RN0:D1a:::or
"or"
*am33
8.0xf9+8.0x19+4.RM2,4.RN0:D1a:::or
"or"
*am33
+*am33_2
{
int srcreg, dstreg;
int z, n;
{
int srcreg, dstreg;
int z, n;
@@
-673,6
+714,7
@@
8.0xf9+8.0x29+4.RM2,4.RN0:D1a:::xor
"xor"
*am33
8.0xf9+8.0x29+4.RM2,4.RN0:D1a:::xor
"xor"
*am33
+*am33_2
{
int srcreg, dstreg;
int z, n;
{
int srcreg, dstreg;
int z, n;
@@
-692,6
+734,7
@@
8.0xf9+8.0x39+4.RM2,4.RN0=RM2:D1:::not
"not"
*am33
8.0xf9+8.0x39+4.RM2,4.RN0=RM2:D1:::not
"not"
*am33
+*am33_2
{
int dstreg;
int z, n;
{
int dstreg;
int z, n;
@@
-710,6
+753,7
@@
8.0xf9+8.0x49+4.RM2,4.RN0:D1a:::asr
"asr"
*am33
8.0xf9+8.0x49+4.RM2,4.RN0:D1a:::asr
"asr"
*am33
+*am33_2
{
int srcreg, dstreg;
signed32 temp;
{
int srcreg, dstreg;
signed32 temp;
@@
-733,6
+777,7
@@
8.0xf9+8.0x59+4.RM2,4.RN0:D1a:::lsr
"lsr"
*am33
8.0xf9+8.0x59+4.RM2,4.RN0:D1a:::lsr
"lsr"
*am33
+*am33_2
{
int srcreg, dstreg;
int z, n, c;
{
int srcreg, dstreg;
int z, n, c;
@@
-754,6
+799,7
@@
8.0xf9+8.0x69+4.RM2,4.RN0:D1a:::asl
"asl"
*am33
8.0xf9+8.0x69+4.RM2,4.RN0:D1a:::asl
"asl"
*am33
+*am33_2
{
int srcreg, dstreg;
int z, n;
{
int srcreg, dstreg;
int z, n;
@@
-773,6
+819,7
@@
8.0xf9+8.0x79+4.RM2,4.RN0=RM2:D1:::asl2
"asl2"
*am33
8.0xf9+8.0x79+4.RM2,4.RN0=RM2:D1:::asl2
"asl2"
*am33
+*am33_2
{
int dstreg;
int n, z;
{
int dstreg;
int n, z;
@@
-791,6
+838,7
@@
8.0xf9+8.0x89+4.RM2,4.RN0=RM2:D1:::ror
"ror"
*am33
8.0xf9+8.0x89+4.RM2,4.RN0=RM2:D1:::ror
"ror"
*am33
+*am33_2
{
int dstreg;
int c, n, z;
{
int dstreg;
int c, n, z;
@@
-815,6
+863,7
@@
8.0xf9+8.0x99+4.RM2,4.RN0=RM2:D1:::rol
"rol"
*am33
8.0xf9+8.0x99+4.RM2,4.RN0=RM2:D1:::rol
"rol"
*am33
+*am33_2
{
int dstreg;
int c, n, z;
{
int dstreg;
int c, n, z;
@@
-839,6
+888,7
@@
8.0xf9+8.0xa9+4.RM2,4.RN0:D1b:::mul
"mul"
*am33
8.0xf9+8.0xa9+4.RM2,4.RN0:D1b:::mul
"mul"
*am33
+*am33_2
{
int srcreg, dstreg;
unsigned64 temp;
{
int srcreg, dstreg;
unsigned64 temp;
@@
-862,6
+912,7
@@
8.0xf9+8.0xb9+4.RM2,4.RN0:D1b:::mulu
"mulu"
*am33
8.0xf9+8.0xb9+4.RM2,4.RN0:D1b:::mulu
"mulu"
*am33
+*am33_2
{
int srcreg, dstreg;
unsigned64 temp;
{
int srcreg, dstreg;
unsigned64 temp;
@@
-885,6
+936,7
@@
8.0xf9+8.0xc9+4.RM2,4.RN0:D1b:::div
"div"
*am33
8.0xf9+8.0xc9+4.RM2,4.RN0:D1b:::div
"div"
*am33
+*am33_2
{
int srcreg, dstreg;
signed64 temp;
{
int srcreg, dstreg;
signed64 temp;
@@
-910,6
+962,7
@@
8.0xf9+8.0xd9+4.RM2,4.RN0:D1b:::divu
"divu"
*am33
8.0xf9+8.0xd9+4.RM2,4.RN0:D1b:::divu
"divu"
*am33
+*am33_2
{
int srcreg, dstreg;
unsigned64 temp;
{
int srcreg, dstreg;
unsigned64 temp;
@@
-936,6
+989,7
@@
8.0xf9+8.0x0a+4.RN2,4.RM0:D1h:::mov
"mov"
*am33
8.0xf9+8.0x0a+4.RN2,4.RM0:D1h:::mov
"mov"
*am33
+*am33_2
{
int srcreg, dstreg;
{
int srcreg, dstreg;
@@
-949,6
+1003,7
@@
8.0xf9+8.0x1a+4.RM2,4.RN0:D1i:::mov
"mov"
*am33
8.0xf9+8.0x1a+4.RM2,4.RN0:D1i:::mov
"mov"
*am33
+*am33_2
{
int srcreg, dstreg;
{
int srcreg, dstreg;
@@
-962,6
+1017,7
@@
8.0xf9+8.0x2a+4.RN2,4.RM0:D1g:::movbu
"movbu"
*am33
8.0xf9+8.0x2a+4.RN2,4.RM0:D1g:::movbu
"movbu"
*am33
+*am33_2
{
int srcreg, dstreg;
{
int srcreg, dstreg;
@@
-975,6
+1031,7
@@
8.0xf9+8.0x3a+4.RM2,4.RN0:D1i:::movbu
"movbu"
*am33
8.0xf9+8.0x3a+4.RM2,4.RN0:D1i:::movbu
"movbu"
*am33
+*am33_2
{
int srcreg, dstreg;
{
int srcreg, dstreg;
@@
-988,6
+1045,7
@@
8.0xf9+8.0x4a+4.RN2,4.RM0:D1g:::movhu
"movhu"
*am33
8.0xf9+8.0x4a+4.RN2,4.RM0:D1g:::movhu
"movhu"
*am33
+*am33_2
{
int srcreg, dstreg;
{
int srcreg, dstreg;
@@
-1001,6
+1059,7
@@
8.0xf9+8.0x5a+4.RM2,4.RN0:D1i:::movhu
"movhu"
*am33
8.0xf9+8.0x5a+4.RM2,4.RN0:D1i:::movhu
"movhu"
*am33
+*am33_2
{
int srcreg, dstreg;
{
int srcreg, dstreg;
@@
-1014,6
+1073,7
@@
8.0xf9+8.0x6a+4.RN2,4.RM0!RN2:D1y:::mov
"mov"
*am33
8.0xf9+8.0x6a+4.RN2,4.RM0!RN2:D1y:::mov
"mov"
*am33
+*am33_2
{
int srcreg, dstreg;
{
int srcreg, dstreg;
@@
-1028,6
+1088,7
@@
8.0xf9+8.0x7a+4.RM2,4.RN0:D1z:::mov
"mov"
*am33
8.0xf9+8.0x7a+4.RM2,4.RN0:D1z:::mov
"mov"
*am33
+*am33_2
{
int srcreg, dstreg;
{
int srcreg, dstreg;
@@
-1042,6
+1103,7
@@
8.0xf9+8.0x8a+4.RN2,4.0000:D1j:::mov
"mov"
*am33
8.0xf9+8.0x8a+4.RN2,4.0000:D1j:::mov
"mov"
*am33
+*am33_2
{
int dstreg;
{
int dstreg;
@@
-1054,6
+1116,7
@@
8.0xf9+8.0x9a+4.RM2,4.0000:D1k:::mov
"mov"
*am33
8.0xf9+8.0x9a+4.RM2,4.0000:D1k:::mov
"mov"
*am33
+*am33_2
{
int srcreg;
{
int srcreg;
@@
-1066,6
+1129,7
@@
8.0xf9+8.0xaa+4.RN2,4.0000:D1j:::movbu
"movbu"
*am33
8.0xf9+8.0xaa+4.RN2,4.0000:D1j:::movbu
"movbu"
*am33
+*am33_2
{
int dstreg;
{
int dstreg;
@@
-1078,6
+1142,7
@@
8.0xf9+8.0xba+4.RM2,4.0000:D1k:::movbu
"movbu"
*am33
8.0xf9+8.0xba+4.RM2,4.0000:D1k:::movbu
"movbu"
*am33
+*am33_2
{
int srcreg;
{
int srcreg;
@@
-1090,6
+1155,7
@@
8.0xf9+8.0xca+4.RN2,4.0000:D1j:::movhu
"movhu"
*am33
8.0xf9+8.0xca+4.RN2,4.0000:D1j:::movhu
"movhu"
*am33
+*am33_2
{
int dstreg;
{
int dstreg;
@@
-1102,6
+1168,7
@@
8.0xf9+8.0xda+4.RM2,4.0000:D1k:::movhu
"movhu"
*am33
8.0xf9+8.0xda+4.RM2,4.0000:D1k:::movhu
"movhu"
*am33
+*am33_2
{
int srcreg;
{
int srcreg;
@@
-1114,6
+1181,7
@@
8.0xf9+8.0xea+4.RN2,4.RM0!RN2:D1y:::movhu
"movhu"
*am33
8.0xf9+8.0xea+4.RN2,4.RM0!RN2:D1y:::movhu
"movhu"
*am33
+*am33_2
{
int srcreg, dstreg;
{
int srcreg, dstreg;
@@
-1128,6
+1196,7
@@
8.0xf9+8.0xfa+4.RM2,4.RN0:D1z:::movhu
"movhu"
*am33
8.0xf9+8.0xfa+4.RM2,4.RN0:D1z:::movhu
"movhu"
*am33
+*am33_2
{
int srcreg, dstreg;
{
int srcreg, dstreg;
@@
-1143,6
+1212,7
@@
8.0xf9+8.0x0b+4.RM2,4.RN0:D1:::mac
"mac"
*am33
8.0xf9+8.0x0b+4.RM2,4.RN0:D1:::mac
"mac"
*am33
+*am33_2
{
int srcreg1, srcreg2;
signed64 temp, sum;
{
int srcreg1, srcreg2;
signed64 temp, sum;
@@
-1171,6
+1241,7
@@
8.0xf9+8.0x1b+4.RM2,4.RN0:D1:::macu
"macu"
*am33
8.0xf9+8.0x1b+4.RM2,4.RN0:D1:::macu
"macu"
*am33
+*am33_2
{
int srcreg1, srcreg2;
unsigned64 temp, sum;
{
int srcreg1, srcreg2;
unsigned64 temp, sum;
@@
-1199,6
+1270,7
@@
8.0xf9+8.0x2b+4.RM2,4.RN0:D1:::macb
"macb"
*am33
8.0xf9+8.0x2b+4.RM2,4.RN0:D1:::macb
"macb"
*am33
+*am33_2
{
int srcreg1, srcreg2;
signed32 temp, sum;
{
int srcreg1, srcreg2;
signed32 temp, sum;
@@
-1222,6
+1294,7
@@
8.0xf9+8.0x3b+4.RM2,4.RN0:D1:::macbu
"macbu"
*am33
8.0xf9+8.0x3b+4.RM2,4.RN0:D1:::macbu
"macbu"
*am33
+*am33_2
{
int srcreg1, srcreg2;
signed64 temp, sum;
{
int srcreg1, srcreg2;
signed64 temp, sum;
@@
-1245,6
+1318,7
@@
8.0xf9+8.0x4b+4.RM2,4.RN0:D1:::mach
"mach"
*am33
8.0xf9+8.0x4b+4.RM2,4.RN0:D1:::mach
"mach"
*am33
+*am33_2
{
int srcreg1, srcreg2;
signed64 temp, sum;
{
int srcreg1, srcreg2;
signed64 temp, sum;
@@
-1273,6
+1347,7
@@
8.0xf9+8.0x5b+4.RM2,4.RN0:D1:::machu
"machu"
*am33
8.0xf9+8.0x5b+4.RM2,4.RN0:D1:::machu
"machu"
*am33
+*am33_2
{
int srcreg1, srcreg2;
signed64 temp, sum;
{
int srcreg1, srcreg2;
signed64 temp, sum;
@@
-1301,6
+1376,7
@@
8.0xf9+8.0x6b+4.RM2,4.RN0:D1:::dmach
"dmach"
*am33
8.0xf9+8.0x6b+4.RM2,4.RN0:D1:::dmach
"dmach"
*am33
+*am33_2
{
int srcreg1, srcreg2;
signed32 temp, temp2, sum;
{
int srcreg1, srcreg2;
signed32 temp, temp2, sum;
@@
-1326,6
+1402,7
@@
8.0xf9+8.0x7b+4.RM2,4.RN0:D1:::dmachu
"dmachu"
*am33
8.0xf9+8.0x7b+4.RM2,4.RN0:D1:::dmachu
"dmachu"
*am33
+*am33_2
{
int srcreg1, srcreg2;
unsigned32 temp, temp2, sum;
{
int srcreg1, srcreg2;
unsigned32 temp, temp2, sum;
@@
-1351,6
+1428,7
@@
8.0xf9+8.0x8b+4.RM2,4.RN0:D1:::dmulh
"dmulh"
*am33
8.0xf9+8.0x8b+4.RM2,4.RN0:D1:::dmulh
"dmulh"
*am33
+*am33_2
{
int srcreg, dstreg;
signed32 temp;
{
int srcreg, dstreg;
signed32 temp;
@@
-1371,6
+1449,7
@@
8.0xf9+8.0x9b+4.RM2,4.RN0:D1:::dumachu
"dmachu"
*am33
8.0xf9+8.0x9b+4.RM2,4.RN0:D1:::dumachu
"dmachu"
*am33
+*am33_2
{
int srcreg, dstreg;
unsigned32 temp;
{
int srcreg, dstreg;
unsigned32 temp;
@@
-1391,6
+1470,7
@@
8.0xf9+8.0xab+4.RM2,4.RN0:D1:::sat16
"sat16"
*am33
8.0xf9+8.0xab+4.RM2,4.RN0:D1:::sat16
"sat16"
*am33
+*am33_2
{
int srcreg, dstreg;
int value, z, n;
{
int srcreg, dstreg;
int value, z, n;
@@
-1418,6
+1498,7
@@
8.0xf9+8.0xbb+4.RM2,4.RN0:D1:::mcste
"mcste"
*am33
8.0xf9+8.0xbb+4.RM2,4.RN0:D1:::mcste
"mcste"
*am33
+*am33_2
{
int srcreg, dstreg;
{
int srcreg, dstreg;
@@
-1515,6
+1596,7
@@
8.0xf9+8.0xcb+4.RM2,4.RN0:D1:::swap
"swap"
*am33
8.0xf9+8.0xcb+4.RM2,4.RN0:D1:::swap
"swap"
*am33
+*am33_2
{
int srcreg, dstreg;
{
int srcreg, dstreg;
@@
-1532,6
+1614,7
@@
8.0xf9+8.0xdb+4.RM2,4.RN0:D1:::swaph
"swaph"
*am33
8.0xf9+8.0xdb+4.RM2,4.RN0:D1:::swaph
"swaph"
*am33
+*am33_2
{
int srcreg, dstreg;
{
int srcreg, dstreg;
@@
-1549,6
+1632,7
@@
8.0xf9+8.0xeb+4.RM2,4.RN0:D1:::swhw
"swhw"
*am33
8.0xf9+8.0xeb+4.RM2,4.RN0:D1:::swhw
"swhw"
*am33
+*am33_2
{
int srcreg, dstreg;
{
int srcreg, dstreg;
@@
-1564,6
+1648,7
@@
8.0xf9+8.0xfb+4.RM2,4.RN0:D1:::bsch
"bsch"
*am33
8.0xf9+8.0xfb+4.RM2,4.RN0:D1:::bsch
"bsch"
*am33
+*am33_2
{
int temp, c, i;
int srcreg, dstreg;
{
int temp, c, i;
int srcreg, dstreg;
@@
-1578,6
+1663,7
@@
if (start == -1)
start = 31;
if (start == -1)
start = 31;
+ c = 0;
for (i = start; i >= 0; i--)
{
if (temp & (1 << i))
for (i = start; i >= 0; i--)
{
if (temp & (1 << i))
@@
-1602,6
+1688,7
@@
8.0xfb+8.0x08+4.RM2,4.RN0=RM2+8.IMM8:D2j:::mov
"mov"
*am33
8.0xfb+8.0x08+4.RM2,4.RN0=RM2+8.IMM8:D2j:::mov
"mov"
*am33
+*am33_2
{
int dstreg;
{
int dstreg;
@@
-1614,6
+1701,7
@@
8.0xfb+8.0x18+4.RM2,4.RN0=RM2+8.IMM8:D2:::movu
"movu"
*am33
8.0xfb+8.0x18+4.RM2,4.RN0=RM2+8.IMM8:D2:::movu
"movu"
*am33
+*am33_2
{
int dstreg;
{
int dstreg;
@@
-1626,6
+1714,7
@@
8.0xfb+8.0x78+4.RM2,4.RN0=RM2+8.IMM8:D2d:::add
"add"
*am33
8.0xfb+8.0x78+4.RM2,4.RN0=RM2+8.IMM8:D2d:::add
"add"
*am33
+*am33_2
{
int dstreg;
{
int dstreg;
@@
-1638,10
+1727,11
@@
8.0xfb+8.0x88+4.RM2,4.RN0=RM2+8.IMM8:D2d:::addc
"addc"
*am33
8.0xfb+8.0x88+4.RM2,4.RN0=RM2+8.IMM8:D2d:::addc
"addc"
*am33
+*am33_2
{
int dstreg, imm;
int z, c, n, v;
{
int dstreg, imm;
int z, c, n, v;
- unsigned32 reg
1, reg
2, sum;
+ unsigned32 reg2, sum;
PC = cia;
dstreg = translate_rreg (SD_, RN0);
PC = cia;
dstreg = translate_rreg (SD_, RN0);
@@
-1666,6
+1756,7
@@
8.0xfb+8.0x98+4.RM2,4.RN0=RM2+8.IMM8:D2d:::sub
"sub"
*am33
8.0xfb+8.0x98+4.RM2,4.RN0=RM2+8.IMM8:D2d:::sub
"sub"
*am33
+*am33_2
{
int dstreg;
{
int dstreg;
@@
-1679,10
+1770,11
@@
8.0xfb+8.0xa8+4.RM2,4.RN0=RM2+8.IMM8:D2d:::subc
"subc"
*am33
8.0xfb+8.0xa8+4.RM2,4.RN0=RM2+8.IMM8:D2d:::subc
"subc"
*am33
+*am33_2
{
int imm, dstreg;
int z, c, n, v;
{
int imm, dstreg;
int z, c, n, v;
- unsigned32 reg
1, reg
2, difference;
+ unsigned32 reg2, difference;
PC = cia;
dstreg = translate_rreg (SD_, RN0);
PC = cia;
dstreg = translate_rreg (SD_, RN0);
@@
-1707,6
+1799,7
@@
8.0xfb+8.0xd8+4.RM2,4.RN0=RM2+8.IMM8:D2b:::cmp
"cmp"
*am33
8.0xfb+8.0xd8+4.RM2,4.RN0=RM2+8.IMM8:D2b:::cmp
"cmp"
*am33
+*am33_2
{
int srcreg;
{
int srcreg;
@@
-1719,6
+1812,7
@@
8.0xfb+8.0xf8+4.XRM2,4.XRN0=XRM2+8.IMM8:D2k:::mov
"mov"
*am33
8.0xfb+8.0xf8+4.XRM2,4.XRN0=XRM2+8.IMM8:D2k:::mov
"mov"
*am33
+*am33_2
{
int dstreg;
{
int dstreg;
@@
-1732,6
+1826,7
@@
8.0xfb+8.0x09+4.RM2,4.RN0=RM2+8.IMM8:D2d:::and
"and"
*am33
8.0xfb+8.0x09+4.RM2,4.RN0=RM2+8.IMM8:D2d:::and
"and"
*am33
+*am33_2
{
int dstreg;
int z, n;
{
int dstreg;
int z, n;
@@
-1750,6
+1845,7
@@
8.0xfb+8.0x19+4.RM2,4.RN0=RM2+8.IMM8:D2d:::or
"or"
*am33
8.0xfb+8.0x19+4.RM2,4.RN0=RM2+8.IMM8:D2d:::or
"or"
*am33
+*am33_2
{
int dstreg;
int z, n;
{
int dstreg;
int z, n;
@@
-1768,6
+1864,7
@@
8.0xfb+8.0x29+4.RM2,4.RN0=RM2+8.IMM8:D2d:::xor
"xor"
*am33
8.0xfb+8.0x29+4.RM2,4.RN0=RM2+8.IMM8:D2d:::xor
"xor"
*am33
+*am33_2
{
int dstreg;
int z, n;
{
int dstreg;
int z, n;
@@
-1786,6
+1883,7
@@
8.0xfb+8.0x49+4.RM2,4.RN0=RM2+8.IMM8:D2a:::asr
"asr"
*am33
8.0xfb+8.0x49+4.RM2,4.RN0=RM2+8.IMM8:D2a:::asr
"asr"
*am33
+*am33_2
{
int dstreg;
signed32 temp;
{
int dstreg;
signed32 temp;
@@
-1808,6
+1906,7
@@
8.0xfb+8.0x59+4.RM2,4.RN0=RM2+8.IMM8:D2a:::lsr
"lsr"
*am33
8.0xfb+8.0x59+4.RM2,4.RN0=RM2+8.IMM8:D2a:::lsr
"lsr"
*am33
+*am33_2
{
int dstreg;
int z, n, c;
{
int dstreg;
int z, n, c;
@@
-1827,8
+1926,9
@@
8.0xfb+8.0x69+4.RM2,4.RN0=RM2+8.IMM8:D2a:::asl
"asl"
*am33
8.0xfb+8.0x69+4.RM2,4.RN0=RM2+8.IMM8:D2a:::asl
"asl"
*am33
+*am33_2
{
{
- int
srcreg,
dstreg;
+ int dstreg;
int z, n;
PC = cia;
int z, n;
PC = cia;
@@
-1845,6
+1945,7
@@
8.0xfb+8.0xa9+4.RM2,4.RN0=RM2+8.IMM8:D2a:::mul
"mul"
*am33
8.0xfb+8.0xa9+4.RM2,4.RN0=RM2+8.IMM8:D2a:::mul
"mul"
*am33
+*am33_2
{
int dstreg;
unsigned64 temp;
{
int dstreg;
unsigned64 temp;
@@
-1867,6
+1968,7
@@
8.0xfb+8.0xb9+4.RM2,4.RN0=RM2+8.IMM8:D2a:::mulu
"mulu"
*am33
8.0xfb+8.0xb9+4.RM2,4.RN0=RM2+8.IMM8:D2a:::mulu
"mulu"
*am33
+*am33_2
{
int dstreg;
unsigned64 temp;
{
int dstreg;
unsigned64 temp;
@@
-1889,6
+1991,7
@@
8.0xfb+8.0xe9+4.RN2,4.RM0=RN2+8.IMM8:D2l:::btst
"btst"
*am33
8.0xfb+8.0xe9+4.RN2,4.RM0=RN2+8.IMM8:D2l:::btst
"btst"
*am33
+*am33_2
{
int srcreg;
{
int srcreg;
@@
-1901,6
+2004,7
@@
8.0xfb+8.0x0a+4.RN2,4.RM0+8.IMM8:D2l:::mov
"mov"
*am33
8.0xfb+8.0x0a+4.RN2,4.RM0+8.IMM8:D2l:::mov
"mov"
*am33
+*am33_2
{
int srcreg, dstreg;
{
int srcreg, dstreg;
@@
-1914,6
+2018,7
@@
8.0xfb+8.0x1a+4.RM2,4.RN0+8.IMM8:D2m:::mov
"mov"
*am33
8.0xfb+8.0x1a+4.RM2,4.RN0+8.IMM8:D2m:::mov
"mov"
*am33
+*am33_2
{
int srcreg, dstreg;
{
int srcreg, dstreg;
@@
-1927,6
+2032,7
@@
8.0xfb+8.0x2a+4.RN2,4.RM0+8.IMM8:D2l:::movbu
"movbu"
*am33
8.0xfb+8.0x2a+4.RN2,4.RM0+8.IMM8:D2l:::movbu
"movbu"
*am33
+*am33_2
{
int srcreg, dstreg;
{
int srcreg, dstreg;
@@
-1940,6
+2046,7
@@
8.0xfb+8.0x3a+4.RM2,4.RN0+8.IMM8:D2m:::movbu
"movbu"
*am33
8.0xfb+8.0x3a+4.RM2,4.RN0+8.IMM8:D2m:::movbu
"movbu"
*am33
+*am33_2
{
int srcreg, dstreg;
{
int srcreg, dstreg;
@@
-1953,6
+2060,7
@@
8.0xfb+8.0x4a+4.RN2,4.RM0+8.IMM8:D2l:::movhu
"movhu"
*am33
8.0xfb+8.0x4a+4.RN2,4.RM0+8.IMM8:D2l:::movhu
"movhu"
*am33
+*am33_2
{
int srcreg, dstreg;
{
int srcreg, dstreg;
@@
-1966,6
+2074,7
@@
8.0xfb+8.0x5a+4.RM2,4.RN0+8.IMM8:D2m:::movhu
"movhu"
*am33
8.0xfb+8.0x5a+4.RM2,4.RN0+8.IMM8:D2m:::movhu
"movhu"
*am33
+*am33_2
{
int srcreg, dstreg;
{
int srcreg, dstreg;
@@
-1979,6
+2088,7
@@
8.0xfb+8.0x6a+4.RN2,4.RM0!RN2+8.IMM8:D2y:::mov
"mov"
*am33
8.0xfb+8.0x6a+4.RN2,4.RM0!RN2+8.IMM8:D2y:::mov
"mov"
*am33
+*am33_2
{
int srcreg, dstreg;
{
int srcreg, dstreg;
@@
-1993,6
+2103,7
@@
8.0xfb+8.0x7a+4.RM2,4.RN0+8.IMM8:D2z:::mov
"mov"
*am33
8.0xfb+8.0x7a+4.RM2,4.RN0+8.IMM8:D2z:::mov
"mov"
*am33
+*am33_2
{
int srcreg, dstreg;
{
int srcreg, dstreg;
@@
-2008,6
+2119,7
@@
8.0xfb+8.0x8a+4.RN2,4.0x0+8.IMM8:D2n:::mov
"mov"
*am33
8.0xfb+8.0x8a+4.RN2,4.0x0+8.IMM8:D2n:::mov
"mov"
*am33
+*am33_2
{
int dstreg;
{
int dstreg;
@@
-2020,6
+2132,7
@@
8.0xfb+8.0x9a+4.RM2,4.0x0+8.IMM8:D2o:::mov
"mov"
*am33
8.0xfb+8.0x9a+4.RM2,4.0x0+8.IMM8:D2o:::mov
"mov"
*am33
+*am33_2
{
int srcreg;
{
int srcreg;
@@
-2032,6
+2145,7
@@
8.0xfb+8.0xaa+4.RN2,4.0x0+8.IMM8:D2n:::movbu
"movbu"
*am33
8.0xfb+8.0xaa+4.RN2,4.0x0+8.IMM8:D2n:::movbu
"movbu"
*am33
+*am33_2
{
int dstreg;
{
int dstreg;
@@
-2044,6
+2158,7
@@
8.0xfb+8.0xba+4.RM2,4.0x0+8.IMM8:D2o:::movbu
"movbu"
*am33
8.0xfb+8.0xba+4.RM2,4.0x0+8.IMM8:D2o:::movbu
"movbu"
*am33
+*am33_2
{
int srcreg;
{
int srcreg;
@@
-2056,6
+2171,7
@@
8.0xfb+8.0xca+4.RN2,4.0x0+8.IMM8:D2n:::movhu
"movhu"
*am33
8.0xfb+8.0xca+4.RN2,4.0x0+8.IMM8:D2n:::movhu
"movhu"
*am33
+*am33_2
{
int dstreg;
{
int dstreg;
@@
-2068,6
+2184,7
@@
8.0xfb+8.0xda+4.RM2,4.0x0+8.IMM8:D2o:::movhu
"movhu"
*am33
8.0xfb+8.0xda+4.RM2,4.0x0+8.IMM8:D2o:::movhu
"movhu"
*am33
+*am33_2
{
int srcreg;
{
int srcreg;
@@
-2080,6
+2197,7
@@
8.0xfb+8.0xea+4.RN2,4.RM0!RN2+8.IMM8:D2y:::movhu
"movhu"
*am33
8.0xfb+8.0xea+4.RN2,4.RM0!RN2+8.IMM8:D2y:::movhu
"movhu"
*am33
+*am33_2
{
int srcreg, dstreg;
{
int srcreg, dstreg;
@@
-2094,6
+2212,7
@@
8.0xfb+8.0xfa+4.RM2,4.RN0+8.IMM8:D2z:::movhu
"movhu"
*am33
8.0xfb+8.0xfa+4.RM2,4.RN0+8.IMM8:D2z:::movhu
"movhu"
*am33
+*am33_2
{
int srcreg, dstreg;
{
int srcreg, dstreg;
@@
-2109,6
+2228,7
@@
8.0xfb+8.0x0b+4.RN2,4.RN0=RN2+8.IMM8:D2:::mac
"mac"
*am33
8.0xfb+8.0x0b+4.RN2,4.RN0=RN2+8.IMM8:D2:::mac
"mac"
*am33
+*am33_2
{
int srcreg;
signed64 temp, sum;
{
int srcreg;
signed64 temp, sum;
@@
-2136,6
+2256,7
@@
8.0xfb+8.0x1b+4.RN2,4.RN0=RN2+8.IMM8:D2:::macu
"macu"
*am33
8.0xfb+8.0x1b+4.RN2,4.RN0=RN2+8.IMM8:D2:::macu
"macu"
*am33
+*am33_2
{
int srcreg;
signed64 temp, sum;
{
int srcreg;
signed64 temp, sum;
@@
-2163,6
+2284,7
@@
8.0xfb+8.0x2b+4.RN2,4.RN0=RN2+8.IMM8:D2:::macb
"macb"
*am33
8.0xfb+8.0x2b+4.RN2,4.RN0=RN2+8.IMM8:D2:::macb
"macb"
*am33
+*am33_2
{
int srcreg;
signed64 temp, sum;
{
int srcreg;
signed64 temp, sum;
@@
-2190,6
+2312,7
@@
8.0xfb+8.0x3b+4.RN2,4.RN0=RN2+8.IMM8:D2:::macbu
"macbu"
*am33
8.0xfb+8.0x3b+4.RN2,4.RN0=RN2+8.IMM8:D2:::macbu
"macbu"
*am33
+*am33_2
{
int srcreg;
signed64 temp, sum;
{
int srcreg;
signed64 temp, sum;
@@
-2217,6
+2340,7
@@
8.0xfb+8.0x4b+4.RN2,4.RN0=RN2+8.IMM8:D2:::mach
"mach"
*am33
8.0xfb+8.0x4b+4.RN2,4.RN0=RN2+8.IMM8:D2:::mach
"mach"
*am33
+*am33_2
{
int srcreg;
signed64 temp, sum;
{
int srcreg;
signed64 temp, sum;
@@
-2244,6
+2368,7
@@
8.0xfb+8.0x5b+4.RN2,4.RN0=RN2+8.IMM8:D2:::machu
"machu"
*am33
8.0xfb+8.0x5b+4.RN2,4.RN0=RN2+8.IMM8:D2:::machu
"machu"
*am33
+*am33_2
{
int srcreg;
signed64 temp, sum;
{
int srcreg;
signed64 temp, sum;
@@
-2271,6
+2396,7
@@
8.0xfb+8.0xbb+4.RN2,4.RN0=RN2+8.IMM8:D2:::mcste
"mcste"
*am33
8.0xfb+8.0xbb+4.RN2,4.RN0=RN2+8.IMM8:D2:::mcste
"mcste"
*am33
+*am33_2
{
int dstreg;
{
int dstreg;
@@
-2367,6
+2493,7
@@
8.0xfb+8.0x7c+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::add
"add"
*am33
8.0xfb+8.0x7c+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::add
"add"
*am33
+*am33_2
{
int z, c, n, v;
unsigned32 sum, source1, source2;
{
int z, c, n, v;
unsigned32 sum, source1, source2;
@@
-2397,6
+2524,7
@@
8.0xfb+8.0x8c+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::addc
"addc"
*am33
8.0xfb+8.0x8c+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::addc
"addc"
*am33
+*am33_2
{
int z, c, n, v;
unsigned32 sum, source1, source2;
{
int z, c, n, v;
unsigned32 sum, source1, source2;
@@
-2427,6
+2555,7
@@
8.0xfb+8.0x9c+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::sub
"sub"
*am33
8.0xfb+8.0x9c+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::sub
"sub"
*am33
+*am33_2
{
int z, c, n, v;
unsigned32 difference, source1, source2;
{
int z, c, n, v;
unsigned32 difference, source1, source2;
@@
-2444,7
+2573,7
@@
z = (difference == 0);
n = (difference & 0x80000000);
z = (difference == 0);
n = (difference & 0x80000000);
- c = (source1 > source
1
);
+ c = (source1 > source
2
);
v = ((source1 & 0x80000000) == (source2 & 0x80000000)
&& (source1 & 0x80000000) != (difference & 0x80000000));
v = ((source1 & 0x80000000) == (source2 & 0x80000000)
&& (source1 & 0x80000000) != (difference & 0x80000000));
@@
-2457,6
+2586,7
@@
8.0xfb+8.0xac+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::subc
"subc"
*am33
8.0xfb+8.0xac+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::subc
"subc"
*am33
+*am33_2
{
int z, c, n, v;
unsigned32 difference, source1, source2;
{
int z, c, n, v;
unsigned32 difference, source1, source2;
@@
-2487,6
+2617,7
@@
8.0xfb+8.0x0d+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::and
"and"
*am33
8.0xfb+8.0x0d+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::and
"and"
*am33
+*am33_2
{
int z, n;
int srcreg1, srcreg2, dstreg;
{
int z, n;
int srcreg1, srcreg2, dstreg;
@@
-2509,6
+2640,7
@@
8.0xfb+8.0x1d+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::or
"or"
*am33
8.0xfb+8.0x1d+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::or
"or"
*am33
+*am33_2
{
int z, n;
int srcreg1, srcreg2, dstreg;
{
int z, n;
int srcreg1, srcreg2, dstreg;
@@
-2531,6
+2663,7
@@
8.0xfb+8.0x2d+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::xor
"xor"
*am33
8.0xfb+8.0x2d+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::xor
"xor"
*am33
+*am33_2
{
int z, n;
int srcreg1, srcreg2, dstreg;
{
int z, n;
int srcreg1, srcreg2, dstreg;
@@
-2553,6
+2686,7
@@
8.0xfb+8.0x4d+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::asr
"asr"
*am33
8.0xfb+8.0x4d+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::asr
"asr"
*am33
+*am33_2
{
int z, c, n;
signed32 temp;
{
int z, c, n;
signed32 temp;
@@
-2579,6
+2713,7
@@
8.0xfb+8.0x5d+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::lsr
"lsr"
*am33
8.0xfb+8.0x5d+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::lsr
"lsr"
*am33
+*am33_2
{
int z, c, n;
int srcreg1, srcreg2, dstreg;
{
int z, c, n;
int srcreg1, srcreg2, dstreg;
@@
-2602,6
+2737,7
@@
8.0xfb+8.0x6d+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::asl
"asl"
*am33
8.0xfb+8.0x6d+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::asl
"asl"
*am33
+*am33_2
{
int z, n;
int srcreg1, srcreg2, dstreg;
{
int z, n;
int srcreg1, srcreg2, dstreg;
@@
-2624,6
+2760,7
@@
8.0xfb+8.0xad+4.RM2,4.RN0+4.RD0,4.RD2!RD0:D2c:::mul
"mul"
*am33
8.0xfb+8.0xad+4.RM2,4.RN0+4.RD0,4.RD2!RD0:D2c:::mul
"mul"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
signed64 temp;
{
int srcreg1, srcreg2, dstreg1, dstreg2;
signed64 temp;
@@
-2651,6
+2788,7
@@
8.0xfb+8.0xbd+4.RM2,4.RN0+4.RD0,4.RD2!RD0:D2c:::mulu
"mulu"
*am33
8.0xfb+8.0xbd+4.RM2,4.RN0+4.RD0,4.RD2!RD0:D2c:::mulu
"mulu"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
signed64 temp;
{
int srcreg1, srcreg2, dstreg1, dstreg2;
signed64 temp;
@@
-2678,6
+2816,7
@@
8.0xfb+8.0x0e+4.RN2,4.0x0+8.IMM8:D2p:::mov
"mov"
*am33
8.0xfb+8.0x0e+4.RN2,4.0x0+8.IMM8:D2p:::mov
"mov"
*am33
+*am33_2
{
int dstreg;
{
int dstreg;
@@
-2690,6
+2829,7
@@
8.0xfb+8.0x1e+4.RM2,4.0x0+8.IMM8:D2q:::mov
"mov"
*am33
8.0xfb+8.0x1e+4.RM2,4.0x0+8.IMM8:D2q:::mov
"mov"
*am33
+*am33_2
{
int srcreg;
{
int srcreg;
@@
-2702,6
+2842,7
@@
8.0xfb+8.0x2e+4.RN2,4.0x0+8.IMM8:D2p:::movbu
"movbu"
*am33
8.0xfb+8.0x2e+4.RN2,4.0x0+8.IMM8:D2p:::movbu
"movbu"
*am33
+*am33_2
{
int dstreg;
{
int dstreg;
@@
-2714,6
+2855,7
@@
8.0xfb+8.0x3e+4.RM2,4.0x0+8.IMM8:D2q:::movbu
"movbu"
*am33
8.0xfb+8.0x3e+4.RM2,4.0x0+8.IMM8:D2q:::movbu
"movbu"
*am33
+*am33_2
{
int srcreg;
{
int srcreg;
@@
-2726,6
+2868,7
@@
8.0xfb+8.0x4e+4.RN2,4.0x0+8.IMM8:D2p:::movhu
"movhu"
*am33
8.0xfb+8.0x4e+4.RN2,4.0x0+8.IMM8:D2p:::movhu
"movhu"
*am33
+*am33_2
{
int dstreg;
{
int dstreg;
@@
-2738,6
+2881,7
@@
8.0xfb+8.0x5e+4.RM2,4.0x0+8.IMM8:D2q:::movhu
"movhu"
*am33
8.0xfb+8.0x5e+4.RM2,4.0x0+8.IMM8:D2q:::movhu
"movhu"
*am33
+*am33_2
{
int srcreg;
{
int srcreg;
@@
-2750,12
+2894,13
@@
8.0xfb+8.0x8e+4.RI0,4.RM0+4.RN0,4.0x0:D2r:::mov
"mov"
*am33
8.0xfb+8.0x8e+4.RI0,4.RM0+4.RN0,4.0x0:D2r:::mov
"mov"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg;
PC = cia;
srcreg1 = translate_rreg (SD_, RM0);
{
int srcreg1, srcreg2, dstreg;
PC = cia;
srcreg1 = translate_rreg (SD_, RM0);
- srcreg
1
= translate_rreg (SD_, RI0);
+ srcreg
2
= translate_rreg (SD_, RI0);
dstreg = translate_rreg (SD_, RN0);
State.regs[dstreg] = load_word (State.regs[srcreg1] + State.regs[srcreg2]);
}
dstreg = translate_rreg (SD_, RN0);
State.regs[dstreg] = load_word (State.regs[srcreg1] + State.regs[srcreg2]);
}
@@
-2764,6
+2909,7
@@
8.0xfb+8.0x9e+4.RI0,4.RN0+4.RM0,4.0x0:D2s:::mov
"mov"
*am33
8.0xfb+8.0x9e+4.RI0,4.RN0+4.RM0,4.0x0:D2s:::mov
"mov"
*am33
+*am33_2
{
int srcreg, dstreg1, dstreg2;
{
int srcreg, dstreg1, dstreg2;
@@
-2778,12
+2924,13
@@
8.0xfb+8.0xae+4.RI0,4.RM0+4.RN0,4.0x0:D2r:::movbu
"movbu"
*am33
8.0xfb+8.0xae+4.RI0,4.RM0+4.RN0,4.0x0:D2r:::movbu
"movbu"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg;
PC = cia;
srcreg1 = translate_rreg (SD_, RM0);
{
int srcreg1, srcreg2, dstreg;
PC = cia;
srcreg1 = translate_rreg (SD_, RM0);
- srcreg
1
= translate_rreg (SD_, RI0);
+ srcreg
2
= translate_rreg (SD_, RI0);
dstreg = translate_rreg (SD_, RN0);
State.regs[dstreg] = load_byte (State.regs[srcreg1] + State.regs[srcreg2]);
}
dstreg = translate_rreg (SD_, RN0);
State.regs[dstreg] = load_byte (State.regs[srcreg1] + State.regs[srcreg2]);
}
@@
-2792,6
+2939,7
@@
8.0xfb+8.0xbe+4.RI0,4.RN0+4.RM0,4.0x0:D2s:::movbu
"movbu"
*am33
8.0xfb+8.0xbe+4.RI0,4.RN0+4.RM0,4.0x0:D2s:::movbu
"movbu"
*am33
+*am33_2
{
int srcreg, dstreg1, dstreg2;
{
int srcreg, dstreg1, dstreg2;
@@
-2806,12
+2954,13
@@
8.0xfb+8.0xce+4.RI0,4.RM0+4.RN0,4.0x0:D2r:::movhu
"movhu"
*am33
8.0xfb+8.0xce+4.RI0,4.RM0+4.RN0,4.0x0:D2r:::movhu
"movhu"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg;
PC = cia;
srcreg1 = translate_rreg (SD_, RM0);
{
int srcreg1, srcreg2, dstreg;
PC = cia;
srcreg1 = translate_rreg (SD_, RM0);
- srcreg
1
= translate_rreg (SD_, RI0);
+ srcreg
2
= translate_rreg (SD_, RI0);
dstreg = translate_rreg (SD_, RN0);
State.regs[dstreg] = load_half (State.regs[srcreg1] + State.regs[srcreg2]);
}
dstreg = translate_rreg (SD_, RN0);
State.regs[dstreg] = load_half (State.regs[srcreg1] + State.regs[srcreg2]);
}
@@
-2820,6
+2969,7
@@
8.0xfb+8.0xde+4.RI0,4.RN0+4.RM0,4.0x0:D2s:::movhu
"movhu"
*am33
8.0xfb+8.0xde+4.RI0,4.RN0+4.RM0,4.0x0:D2s:::movhu
"movhu"
*am33
+*am33_2
{
int srcreg, dstreg1, dstreg2;
{
int srcreg, dstreg1, dstreg2;
@@
-2834,6
+2984,7
@@
8.0xfb+8.0x0f+4.RM2,4.RN0+4.RD0,4.RD2!RD0:D2c:::mac
"mac"
*am33
8.0xfb+8.0x0f+4.RM2,4.RN0+4.RD0,4.RD2!RD0:D2c:::mac
"mac"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
signed64 temp;
{
int srcreg1, srcreg2, dstreg1, dstreg2;
signed64 temp;
@@
-2870,6
+3021,7
@@
8.0xfb+8.0x1f+4.RM2,4.RN0+4.RD0,4.RD2!RD0:D2c:::macu
"macu"
*am33
8.0xfb+8.0x1f+4.RM2,4.RN0+4.RD0,4.RD2!RD0:D2c:::macu
"macu"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
signed64 temp;
{
int srcreg1, srcreg2, dstreg1, dstreg2;
signed64 temp;
@@
-2906,6
+3058,7
@@
8.0xfb+8.0x2f+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::macb
"macb"
*am33
8.0xfb+8.0x2f+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::macb
"macb"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg;
signed32 temp, sum;
{
int srcreg1, srcreg2, dstreg;
signed32 temp, sum;
@@
-2934,6
+3087,7
@@
8.0xfb+8.0x3f+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::macbu
"macbu"
*am33
8.0xfb+8.0x3f+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::macbu
"macbu"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg;
signed32 temp, sum;
{
int srcreg1, srcreg2, dstreg;
signed32 temp, sum;
@@
-2962,6
+3116,7
@@
8.0xfb+8.0x4f+4.RM2,4.RN0+4.RD0,4.RD2!RD0:D2c:::mach
"mach"
*am33
8.0xfb+8.0x4f+4.RM2,4.RN0+4.RD0,4.RD2!RD0:D2c:::mach
"mach"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
signed64 temp, sum;
{
int srcreg1, srcreg2, dstreg1, dstreg2;
signed64 temp, sum;
@@
-2992,6
+3147,7
@@
8.0xfb+8.0x5f+4.RM2,4.RN0+4.RD0,4.RD2!RD0:D2c:::machu
"machu"
*am33
8.0xfb+8.0x5f+4.RM2,4.RN0+4.RD0,4.RD2!RD0:D2c:::machu
"machu"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
signed64 temp, sum;
{
int srcreg1, srcreg2, dstreg1, dstreg2;
signed64 temp, sum;
@@
-3022,6
+3178,7
@@
8.0xfb+8.0x6f+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::dmach
"dmach"
*am33
8.0xfb+8.0x6f+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::dmach
"dmach"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg;
signed32 temp, temp2, sum;
{
int srcreg1, srcreg2, dstreg;
signed32 temp, temp2, sum;
@@
-3052,6
+3209,7
@@
8.0xfb+8.0x7f+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::dmachu
"dmachu"
*am33
8.0xfb+8.0x7f+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::dmachu
"dmachu"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg;
signed32 temp, temp2, sum;
{
int srcreg1, srcreg2, dstreg;
signed32 temp, temp2, sum;
@@
-3082,6
+3240,7
@@
8.0xfb+8.0x8f+4.RM2,4.RN0+4.RD0,4.RD2!RD0:D2c:::dmulh
"dmulh"
*am33
8.0xfb+8.0x8f+4.RM2,4.RN0+4.RD0,4.RD2!RD0:D2c:::dmulh
"dmulh"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
signed64 temp;
{
int srcreg1, srcreg2, dstreg1, dstreg2;
signed64 temp;
@@
-3104,6
+3263,7
@@
8.0xfb+8.0x9f+4.RM2,4.RN0+4.RD0,4.RD2!RD0:D2c:::dmulhu
"dmulhu"
*am33
8.0xfb+8.0x9f+4.RM2,4.RN0+4.RD0,4.RD2!RD0:D2c:::dmulhu
"dmulhu"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
signed64 temp;
{
int srcreg1, srcreg2, dstreg1, dstreg2;
signed64 temp;
@@
-3126,6
+3286,7
@@
8.0xfb+8.0xaf+4.RM2,4.RN0+8.0x0:D2:::sat24
"sat24"
*am33
8.0xfb+8.0xaf+4.RM2,4.RN0+8.0x0:D2:::sat24
"sat24"
*am33
+*am33_2
{
int srcreg, dstreg;
int value, n, z;
{
int srcreg, dstreg;
int value, n, z;
@@
-3153,6
+3314,7
@@
8.0xfb+8.0xff+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::bsch
"bsch"
*am33
8.0xfb+8.0xff+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::bsch
"bsch"
*am33
+*am33_2
{
int temp, c, i;
int srcreg1, srcreg2, dstreg;
{
int temp, c, i;
int srcreg1, srcreg2, dstreg;
@@
-3167,7
+3329,8
@@
start = (State.regs[srcreg2] & 0x1f) - 1;
if (start == -1)
start = 31;
start = (State.regs[srcreg2] & 0x1f) - 1;
if (start == -1)
start = 31;
-
+
+ c = 0;
for (i = start; i >= 0; i--)
{
if (temp & (1 << i))
for (i = start; i >= 0; i--)
{
if (temp & (1 << i))
@@
-3191,6
+3354,7
@@
8.0xfd+8.0x08+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4t:::mov
"mov"
*am33
8.0xfd+8.0x08+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4t:::mov
"mov"
*am33
+*am33_2
{
int dstreg;
{
int dstreg;
@@
-3203,6
+3367,7
@@
8.0xfd+8.0x18+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4k:::movu
"movu"
*am33
8.0xfd+8.0x18+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4k:::movu
"movu"
*am33
+*am33_2
{
int dstreg;
{
int dstreg;
@@
-3215,6
+3380,7
@@
8.0xfd+8.0x78+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4c:::add
"add"
*am33
8.0xfd+8.0x78+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4c:::add
"add"
*am33
+*am33_2
{
int dstreg;
{
int dstreg;
@@
-3227,6
+3393,7
@@
8.0xfd+8.0x88+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::addc
"addc"
*am33
8.0xfd+8.0x88+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::addc
"addc"
*am33
+*am33_2
{
int dstreg, z, n, c, v;
unsigned32 sum, imm, reg2;
{
int dstreg, z, n, c, v;
unsigned32 sum, imm, reg2;
@@
-3254,6
+3421,7
@@
8.0xfd+8.0x98+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::sub
"sub"
*am33
8.0xfd+8.0x98+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::sub
"sub"
*am33
+*am33_2
{
int dstreg;
{
int dstreg;
@@
-3266,6
+3434,7
@@
8.0xfd+8.0xa8+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::subc
"subc"
*am33
8.0xfd+8.0xa8+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::subc
"subc"
*am33
+*am33_2
{
int dstreg, z, n, c, v;
unsigned32 difference, imm, reg2;
{
int dstreg, z, n, c, v;
unsigned32 difference, imm, reg2;
@@
-3293,6
+3462,7
@@
8.0xfd+8.0xd8+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::cmp
"cmp"
*am33
8.0xfd+8.0xd8+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::cmp
"cmp"
*am33
+*am33_2
{
int srcreg;
{
int srcreg;
@@
-3305,6
+3475,7
@@
8.0xfd+8.0xf8+4.XRM2,4.XRN0=XRM2+8.IMM24A+8.IMM24B+8.IMM24C:D4o:::mov
"mov"
*am33
8.0xfd+8.0xf8+4.XRM2,4.XRN0=XRM2+8.IMM24A+8.IMM24B+8.IMM24C:D4o:::mov
"mov"
*am33
+*am33_2
{
int dstreg;
{
int dstreg;
@@
-3318,6
+3489,7
@@
8.0xfd+8.0x09+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::and
"and"
*am33
8.0xfd+8.0x09+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::and
"and"
*am33
+*am33_2
{
int dstreg;
int z,n;
{
int dstreg;
int z,n;
@@
-3336,6
+3508,7
@@
8.0xfd+8.0x19+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::or
"or"
*am33
8.0xfd+8.0x19+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::or
"or"
*am33
+*am33_2
{
int dstreg;
int z,n;
{
int dstreg;
int z,n;
@@
-3354,6
+3527,7
@@
8.0xfd+8.0x29+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::xor
"xor"
*am33
8.0xfd+8.0x29+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::xor
"xor"
*am33
+*am33_2
{
int dstreg;
int z,n;
{
int dstreg;
int z,n;
@@
-3372,6
+3546,7
@@
8.0xfd+8.0x49+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::asr
"asr"
*am33
8.0xfd+8.0x49+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::asr
"asr"
*am33
+*am33_2
{
int dstreg;
signed32 temp;
{
int dstreg;
signed32 temp;
@@
-3395,6
+3570,7
@@
8.0xfd+8.0x59+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::lsr
"lsr"
*am33
8.0xfd+8.0x59+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::lsr
"lsr"
*am33
+*am33_2
{
int dstreg;
int z, n, c;
{
int dstreg;
int z, n, c;
@@
-3414,8
+3590,9
@@
8.0xfd+8.0x69+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::asl
"asl"
*am33
8.0xfd+8.0x69+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::asl
"asl"
*am33
+*am33_2
{
{
- int
srcreg,
dstreg;
+ int dstreg;
int z, n;
PC = cia;
int z, n;
PC = cia;
@@
-3432,6
+3609,7
@@
8.0xfd+8.0xa9+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::mul
"mul"
*am33
8.0xfd+8.0xa9+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::mul
"mul"
*am33
+*am33_2
{
int dstreg;
unsigned64 temp;
{
int dstreg;
unsigned64 temp;
@@
-3454,6
+3632,7
@@
8.0xfd+8.0xb9+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::mulu
"mulu"
*am33
8.0xfd+8.0xb9+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::mulu
"mulu"
*am33
+*am33_2
{
int dstreg;
unsigned64 temp;
{
int dstreg;
unsigned64 temp;
@@
-3476,6
+3655,7
@@
8.0xfd+8.0xe9+4.RN2,4.RN0=RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4p:::btst
"btst"
*am33
8.0xfd+8.0xe9+4.RN2,4.RN0=RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4p:::btst
"btst"
*am33
+*am33_2
{
int srcreg;
{
int srcreg;
@@
-3488,6
+3668,7
@@
8.0xfd+8.0x0a+4.RN2,4.RM0+8.IMM24A+8.IMM24B+8.IMM24C:D4p:::mov
"mov"
*am33
8.0xfd+8.0x0a+4.RN2,4.RM0+8.IMM24A+8.IMM24B+8.IMM24C:D4p:::mov
"mov"
*am33
+*am33_2
{
int srcreg, dstreg;
{
int srcreg, dstreg;
@@
-3503,6
+3684,7
@@
8.0xfd+8.0x1a+4.RM2,4.RN0+8.IMM24A+8.IMM24B+8.IMM24C:D4q:::mov
"mov"
*am33
8.0xfd+8.0x1a+4.RM2,4.RN0+8.IMM24A+8.IMM24B+8.IMM24C:D4q:::mov
"mov"
*am33
+*am33_2
{
int srcreg, dstreg;
{
int srcreg, dstreg;
@@
-3517,6
+3699,7
@@
8.0xfd+8.0x2a+4.RN2,4.RM0+8.IMM24A+8.IMM24B+8.IMM24C:D4p:::movbu
"movbu"
*am33
8.0xfd+8.0x2a+4.RN2,4.RM0+8.IMM24A+8.IMM24B+8.IMM24C:D4p:::movbu
"movbu"
*am33
+*am33_2
{
int srcreg, dstreg;
{
int srcreg, dstreg;
@@
-3532,6
+3715,7
@@
8.0xfd+8.0x3a+4.RM2,4.RN0+8.IMM24A+8.IMM24B+8.IMM24C:D4q:::movbu
"movbu"
*am33
8.0xfd+8.0x3a+4.RM2,4.RN0+8.IMM24A+8.IMM24B+8.IMM24C:D4q:::movbu
"movbu"
*am33
+*am33_2
{
int srcreg, dstreg;
{
int srcreg, dstreg;
@@
-3546,6
+3730,7
@@
8.0xfd+8.0x4a+4.RN2,4.RM0+8.IMM24A+8.IMM24B+8.IMM24C:D4p:::movhu
"movhu"
*am33
8.0xfd+8.0x4a+4.RN2,4.RM0+8.IMM24A+8.IMM24B+8.IMM24C:D4p:::movhu
"movhu"
*am33
+*am33_2
{
int srcreg, dstreg;
{
int srcreg, dstreg;
@@
-3561,6
+3746,7
@@
8.0xfd+8.0x5a+4.RM2,4.RN0+8.IMM24A+8.IMM24B+8.IMM24C:D4q:::movhu
"movhu"
*am33
8.0xfd+8.0x5a+4.RM2,4.RN0+8.IMM24A+8.IMM24B+8.IMM24C:D4q:::movhu
"movhu"
*am33
+*am33_2
{
int srcreg, dstreg;
{
int srcreg, dstreg;
@@
-3575,6
+3761,7
@@
8.0xfd+8.0x6a+4.RN2,4.RM0!RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4y:::mov
"mov"
*am33
8.0xfd+8.0x6a+4.RN2,4.RM0!RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4y:::mov
"mov"
*am33
+*am33_2
{
int srcreg, dstreg;
{
int srcreg, dstreg;
@@
-3589,6
+3776,7
@@
8.0xfd+8.0x7a+4.RM2,4.RN0+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::mov
"mov"
*am33
8.0xfd+8.0x7a+4.RM2,4.RN0+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::mov
"mov"
*am33
+*am33_2
{
int srcreg, dstreg;
{
int srcreg, dstreg;
@@
-3604,6
+3792,7
@@
8.0xfd+8.0x8a+4.RN2,4.0x0+IMM24A+8.IMM24B+8.IMM24C:D4r:::mov
"mov"
*am33
8.0xfd+8.0x8a+4.RN2,4.0x0+IMM24A+8.IMM24B+8.IMM24C:D4r:::mov
"mov"
*am33
+*am33_2
{
int dstreg;
{
int dstreg;
@@
-3617,6
+3806,7
@@
8.0xfd+8.0x9a+4.RM2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4s:::mov
"mov"
*am33
8.0xfd+8.0x9a+4.RM2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4s:::mov
"mov"
*am33
+*am33_2
{
int srcreg;
{
int srcreg;
@@
-3630,6
+3820,7
@@
8.0xfd+8.0xaa+4.RN2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4r:::movbu
"movbu"
*am33
8.0xfd+8.0xaa+4.RN2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4r:::movbu
"movbu"
*am33
+*am33_2
{
int dstreg;
{
int dstreg;
@@
-3643,6
+3834,7
@@
8.0xfd+8.0xba+4.RM2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4s:::movbu
"movbu"
*am33
8.0xfd+8.0xba+4.RM2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4s:::movbu
"movbu"
*am33
+*am33_2
{
int srcreg;
{
int srcreg;
@@
-3656,6
+3848,7
@@
8.0xfd+8.0xca+4.RN2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4r:::movhu
"movhu"
*am33
8.0xfd+8.0xca+4.RN2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4r:::movhu
"movhu"
*am33
+*am33_2
{
int dstreg;
{
int dstreg;
@@
-3669,6
+3862,7
@@
8.0xfd+8.0xda+4.RM2,4.RN0+8.IMM24A+8.IMM24B+8.IMM24C:D4s:::movhu
"movhu"
*am33
8.0xfd+8.0xda+4.RM2,4.RN0+8.IMM24A+8.IMM24B+8.IMM24C:D4s:::movhu
"movhu"
*am33
+*am33_2
{
int srcreg;
{
int srcreg;
@@
-3682,6
+3876,7
@@
8.0xfd+8.0xea+4.RN2,4.RM0!RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4y:::movhu
"movhu"
*am33
8.0xfd+8.0xea+4.RN2,4.RM0!RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4y:::movhu
"movhu"
*am33
+*am33_2
{
int srcreg, dstreg;
{
int srcreg, dstreg;
@@
-3696,6
+3891,7
@@
8.0xfd+8.0xfa+4.RM2,4.RN0+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::movhu
"movhu"
*am33
8.0xfd+8.0xfa+4.RM2,4.RN0+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::movhu
"movhu"
*am33
+*am33_2
{
int srcreg, dstreg;
{
int srcreg, dstreg;
@@
-3710,6
+3906,7
@@
8.0xfd+8.0x0b+4.RN2,4.RN0=RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::mac
"mac"
*am33
8.0xfd+8.0x0b+4.RN2,4.RN0=RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::mac
"mac"
*am33
+*am33_2
{
int srcreg;
signed64 temp, sum;
{
int srcreg;
signed64 temp, sum;
@@
-3737,6
+3934,7
@@
8.0xfd+8.0x1b+4.RN2,4.RN0=RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::macu
"macu"
*am33
8.0xfd+8.0x1b+4.RN2,4.RN0=RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::macu
"macu"
*am33
+*am33_2
{
int srcreg;
signed64 temp, sum;
{
int srcreg;
signed64 temp, sum;
@@
-3764,6
+3962,7
@@
8.0xfd+8.0x2b+4.RN2,4.RN0=RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::macb
"macb"
*am33
8.0xfd+8.0x2b+4.RN2,4.RN0=RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::macb
"macb"
*am33
+*am33_2
{
int srcreg;
signed64 temp, sum;
{
int srcreg;
signed64 temp, sum;
@@
-3791,6
+3990,7
@@
8.0xfd+8.0x3b+4.RN2,4.RN0=RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::macbu
"macbu"
*am33
8.0xfd+8.0x3b+4.RN2,4.RN0=RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::macbu
"macbu"
*am33
+*am33_2
{
int srcreg;
signed64 temp, sum;
{
int srcreg;
signed64 temp, sum;
@@
-3818,6
+4018,7
@@
8.0xfd+8.0x4b+4.RN2,4.RN0=RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::mach
"mach"
*am33
8.0xfd+8.0x4b+4.RN2,4.RN0=RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::mach
"mach"
*am33
+*am33_2
{
int srcreg;
signed64 temp, sum;
{
int srcreg;
signed64 temp, sum;
@@
-3845,6
+4046,7
@@
8.0xfd+8.0x5b+4.RN2,4.RN0=RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::machu
"machu"
*am33
8.0xfd+8.0x5b+4.RN2,4.RN0=RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::machu
"machu"
*am33
+*am33_2
{
int srcreg;
signed64 temp, sum;
{
int srcreg;
signed64 temp, sum;
@@
-3872,6
+4074,7
@@
8.0xfd+8.0x0e+4.RN2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4u:::mov
"mov"
*am33
8.0xfd+8.0x0e+4.RN2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4u:::mov
"mov"
*am33
+*am33_2
{
int dstreg;
{
int dstreg;
@@
-3884,6
+4087,7
@@
8.0xfd+8.0x1e+4.RM2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4v:::mov
"mov"
*am33
8.0xfd+8.0x1e+4.RM2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4v:::mov
"mov"
*am33
+*am33_2
{
int srcreg;
{
int srcreg;
@@
-3897,6
+4101,7
@@
8.0xfd+8.0x2e+4.RN2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4t:::movbu
"movbu"
*am33
8.0xfd+8.0x2e+4.RN2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4t:::movbu
"movbu"
*am33
+*am33_2
{
int dstreg;
{
int dstreg;
@@
-3909,6
+4114,7
@@
8.0xfd+8.0x3e+4.RM2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4u:::movbu
"movbu"
*am33
8.0xfd+8.0x3e+4.RM2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4u:::movbu
"movbu"
*am33
+*am33_2
{
int srcreg;
{
int srcreg;
@@
-3922,6
+4128,7
@@
8.0xfd+8.0x4e+4.RN2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4t:::movhu
"movhu"
*am33
8.0xfd+8.0x4e+4.RN2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4t:::movhu
"movhu"
*am33
+*am33_2
{
int dstreg;
{
int dstreg;
@@
-3934,6
+4141,7
@@
8.0xfd+8.0x5e+4.RM2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4u:::movhu
"movhu"
*am33
8.0xfd+8.0x5e+4.RM2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4u:::movhu
"movhu"
*am33
+*am33_2
{
int srcreg;
{
int srcreg;
@@
-3947,6
+4155,7
@@
8.0xfe+8.0x08+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::mov
"mov"
*am33
8.0xfe+8.0x08+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::mov
"mov"
*am33
+*am33_2
{
int dstreg;
{
int dstreg;
@@
-3959,6
+4168,7
@@
8.0xfe+8.0x18+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::movu
"movu"
*am33
8.0xfe+8.0x18+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::movu
"movu"
*am33
+*am33_2
{
int dstreg;
{
int dstreg;
@@
-3971,6
+4181,7
@@
8.0xfe+8.0x78+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::add
"add"
*am33
8.0xfe+8.0x78+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::add
"add"
*am33
+*am33_2
{
int dstreg;
{
int dstreg;
@@
-3983,6
+4194,7
@@
8.0xfe+8.0x88+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::addc
"addc"
*am33
8.0xfe+8.0x88+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::addc
"addc"
*am33
+*am33_2
{
int dstreg;
unsigned32 imm, reg2, sum;
{
int dstreg;
unsigned32 imm, reg2, sum;
@@
-4011,6
+4223,7
@@
8.0xfe+8.0x98+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::sub
"sub"
*am33
8.0xfe+8.0x98+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::sub
"sub"
*am33
+*am33_2
{
int dstreg;
{
int dstreg;
@@
-4023,6
+4236,7
@@
8.0xfe+8.0xa8+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::subc
"subc"
*am33
8.0xfe+8.0xa8+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::subc
"subc"
*am33
+*am33_2
{
int dstreg;
unsigned32 imm, reg2, difference;
{
int dstreg;
unsigned32 imm, reg2, difference;
@@
-4051,6
+4265,7
@@
8.0xfe+8.0xd8+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::cmp
"cmp"
*am33
8.0xfe+8.0xd8+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::cmp
"cmp"
*am33
+*am33_2
{
int srcreg;
{
int srcreg;
@@
-4063,6
+4278,7
@@
8.0xfe+8.0xf8+4.XRM2,4.XRN0=XRM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5b:::mov
"mov"
*am33
8.0xfe+8.0xf8+4.XRM2,4.XRN0=XRM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5b:::mov
"mov"
*am33
+*am33_2
{
int dstreg;
{
int dstreg;
@@
-4076,6
+4292,7
@@
8.0xfe+8.0x09+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::and
"and"
*am33
8.0xfe+8.0x09+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::and
"and"
*am33
+*am33_2
{
int dstreg;
int z,n;
{
int dstreg;
int z,n;
@@
-4094,6
+4311,7
@@
8.0xfe+8.0x19+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::or
"or"
*am33
8.0xfe+8.0x19+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::or
"or"
*am33
+*am33_2
{
int dstreg;
int z,n;
{
int dstreg;
int z,n;
@@
-4112,6
+4330,7
@@
8.0xfe+8.0x29+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::xor
"xor"
*am33
8.0xfe+8.0x29+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::xor
"xor"
*am33
+*am33_2
{
int dstreg;
int z,n;
{
int dstreg;
int z,n;
@@
-4130,6
+4349,7
@@
8.0xfe+8.0x49+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::asr
"asr"
*am33
8.0xfe+8.0x49+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::asr
"asr"
*am33
+*am33_2
{
int dstreg;
signed32 temp;
{
int dstreg;
signed32 temp;
@@
-4152,6
+4372,7
@@
8.0xfe+8.0x59+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::lsr
"lsr"
*am33
8.0xfe+8.0x59+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::lsr
"lsr"
*am33
+*am33_2
{
int dstreg;
int z, n, c;
{
int dstreg;
int z, n, c;
@@
-4171,8
+4392,9
@@
8.0xfe+8.0x69+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::asl
"asl"
*am33
8.0xfe+8.0x69+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::asl
"asl"
*am33
+*am33_2
{
{
- int
srcreg,
dstreg;
+ int dstreg;
int z, n;
PC = cia;
int z, n;
PC = cia;
@@
-4189,6
+4411,7
@@
8.0xfe+8.0xa9+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::mul
"mul"
*am33
8.0xfe+8.0xa9+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::mul
"mul"
*am33
+*am33_2
{
int dstreg;
unsigned64 temp;
{
int dstreg;
unsigned64 temp;
@@
-4211,6
+4434,7
@@
8.0xfe+8.0xb9+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::mulu
"mulu"
*am33
8.0xfe+8.0xb9+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::mulu
"mulu"
*am33
+*am33_2
{
int dstreg;
unsigned64 temp;
{
int dstreg;
unsigned64 temp;
@@
-4233,6
+4457,7
@@
8.0xfe+8.0xe9+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5a:::btst
"btst"
*am33
8.0xfe+8.0xe9+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5a:::btst
"btst"
*am33
+*am33_2
{
int srcreg;
{
int srcreg;
@@
-4245,6
+4470,7
@@
8.0xfe+8.0x0a+4.RN2,4.RM0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5f:::mov
"mov"
*am33
8.0xfe+8.0x0a+4.RN2,4.RM0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5f:::mov
"mov"
*am33
+*am33_2
{
int srcreg, dstreg;
{
int srcreg, dstreg;
@@
-4259,6
+4485,7
@@
8.0xfe+8.0x1a+4.RM2,4.RN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5g:::mov
"mov"
*am33
8.0xfe+8.0x1a+4.RM2,4.RN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5g:::mov
"mov"
*am33
+*am33_2
{
int srcreg, dstreg;
{
int srcreg, dstreg;
@@
-4273,6
+4500,7
@@
8.0xfe+8.0x2a+4.RN2,4.RM0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::movbu
"movbu"
*am33
8.0xfe+8.0x2a+4.RN2,4.RM0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::movbu
"movbu"
*am33
+*am33_2
{
int srcreg, dstreg;
{
int srcreg, dstreg;
@@
-4287,6
+4515,7
@@
8.0xfe+8.0x3a+4.RM2,4.RN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5b:::movbu
"movbu"
*am33
8.0xfe+8.0x3a+4.RM2,4.RN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5b:::movbu
"movbu"
*am33
+*am33_2
{
int srcreg, dstreg;
{
int srcreg, dstreg;
@@
-4301,6
+4530,7
@@
8.0xfe+8.0x4a+4.RN2,4.RM0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::movhu
"movhu"
*am33
8.0xfe+8.0x4a+4.RN2,4.RM0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::movhu
"movhu"
*am33
+*am33_2
{
int srcreg, dstreg;
{
int srcreg, dstreg;
@@
-4315,6
+4545,7
@@
8.0xfe+8.0x5a+4.RM2,4.RN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5b:::movhu
"movhu"
*am33
8.0xfe+8.0x5a+4.RM2,4.RN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5b:::movhu
"movhu"
*am33
+*am33_2
{
int srcreg, dstreg;
{
int srcreg, dstreg;
@@
-4329,6
+4560,7
@@
8.0xfe+8.0x6a+4.RN2,4.RM0!RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5y:::mov
"mov"
*am33
8.0xfe+8.0x6a+4.RN2,4.RM0!RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5y:::mov
"mov"
*am33
+*am33_2
{
int srcreg, dstreg;
{
int srcreg, dstreg;
@@
-4343,6
+4575,7
@@
8.0xfe+8.0x7a+4.RM2,4.RN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5z:::mov
"mov"
*am33
8.0xfe+8.0x7a+4.RM2,4.RN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5z:::mov
"mov"
*am33
+*am33_2
{
int srcreg, dstreg;
{
int srcreg, dstreg;
@@
-4358,6
+4591,7
@@
8.0xfe+8.0x8a+4.RN2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5c:::mov
"mov"
*am33
8.0xfe+8.0x8a+4.RN2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5c:::mov
"mov"
*am33
+*am33_2
{
int dstreg;
{
int dstreg;
@@
-4371,6
+4605,7
@@
8.0xfe+8.0x9a+4.RM2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5d:::mov
"mov"
*am33
8.0xfe+8.0x9a+4.RM2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5d:::mov
"mov"
*am33
+*am33_2
{
int srcreg;
{
int srcreg;
@@
-4384,6
+4619,7
@@
8.0xfe+8.0xaa+4.RN2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5c:::movbu
"movbu"
*am33
8.0xfe+8.0xaa+4.RN2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5c:::movbu
"movbu"
*am33
+*am33_2
{
int dstreg;
{
int dstreg;
@@
-4397,6
+4633,7
@@
8.0xfe+8.0xba+4.RM2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5d:::movbu
"movbu"
*am33
8.0xfe+8.0xba+4.RM2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5d:::movbu
"movbu"
*am33
+*am33_2
{
int srcreg;
{
int srcreg;
@@
-4410,6
+4647,7
@@
8.0xfe+8.0xca+4.RN2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5c:::movhu
"movhu"
*am33
8.0xfe+8.0xca+4.RN2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5c:::movhu
"movhu"
*am33
+*am33_2
{
int dstreg;
{
int dstreg;
@@
-4423,6
+4661,7
@@
8.0xfe+8.0xda+4.RM2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5d:::movhu
"movhu"
*am33
8.0xfe+8.0xda+4.RM2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5d:::movhu
"movhu"
*am33
+*am33_2
{
int srcreg;
{
int srcreg;
@@
-4437,6
+4676,7
@@
8.0xfe+8.0xea+4.RN2,4.RM0!RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5y:::movhu
"movhu"
*am33
8.0xfe+8.0xea+4.RN2,4.RM0!RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5y:::movhu
"movhu"
*am33
+*am33_2
{
int srcreg, dstreg;
{
int srcreg, dstreg;
@@
-4451,6
+4691,7
@@
8.0xfe+8.0xfa+4.RM2,4.RN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5f:::movhu
"movhu"
*am33
8.0xfe+8.0xfa+4.RM2,4.RN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5f:::movhu
"movhu"
*am33
+*am33_2
{
int srcreg, dstreg;
{
int srcreg, dstreg;
@@
-4466,6
+4707,7
@@
8.0xfe+8.0x0b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::mac
"mac"
*am33
8.0xfe+8.0x0b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::mac
"mac"
*am33
+*am33_2
{
int srcreg, imm;
signed64 temp, sum;
{
int srcreg, imm;
signed64 temp, sum;
@@
-4494,6
+4736,7
@@
8.0xfe+8.0x1b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::macu
"macu"
*am33
8.0xfe+8.0x1b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::macu
"macu"
*am33
+*am33_2
{
int srcreg, imm;
signed64 temp, sum;
{
int srcreg, imm;
signed64 temp, sum;
@@
-4522,6
+4765,7
@@
8.0xfe+8.0x2b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::macb
"macb"
*am33
8.0xfe+8.0x2b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::macb
"macb"
*am33
+*am33_2
{
int srcreg, imm;
signed32 temp, sum;
{
int srcreg, imm;
signed32 temp, sum;
@@
-4545,6
+4789,7
@@
8.0xfe+8.0x3b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::macbu
"macbu"
*am33
8.0xfe+8.0x3b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::macbu
"macbu"
*am33
+*am33_2
{
int srcreg, imm;
signed32 temp, sum;
{
int srcreg, imm;
signed32 temp, sum;
@@
-4568,6
+4813,7
@@
8.0xfe+8.0x4b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::mach
"mach"
*am33
8.0xfe+8.0x4b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::mach
"mach"
*am33
+*am33_2
{
int srcreg, imm;
signed32 temp, sum;
{
int srcreg, imm;
signed32 temp, sum;
@@
-4591,6
+4837,7
@@
8.0xfe+8.0x5b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::machu
"machu"
*am33
8.0xfe+8.0x5b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::machu
"machu"
*am33
+*am33_2
{
int srcreg, imm;
signed32 temp, sum;
{
int srcreg, imm;
signed32 temp, sum;
@@
-4614,6
+4861,7
@@
8.0xfe+8.0x6b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::dmach
"dmach"
*am33
8.0xfe+8.0x6b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::dmach
"dmach"
*am33
+*am33_2
{
int srcreg, imm;
signed32 temp, temp2, sum;
{
int srcreg, imm;
signed32 temp, temp2, sum;
@@
-4639,6
+4887,7
@@
8.0xfe+8.0x7b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::dmachu
"dmachu"
*am33
8.0xfe+8.0x7b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::dmachu
"dmachu"
*am33
+*am33_2
{
int srcreg, imm;
signed32 temp, temp2, sum;
{
int srcreg, imm;
signed32 temp, temp2, sum;
@@
-4664,6
+4913,7
@@
8.0xfe+8.0x8b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::dmulh
"dmulh"
*am33
8.0xfe+8.0x8b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::dmulh
"dmulh"
*am33
+*am33_2
{
int imm, dstreg;
signed32 temp;
{
int imm, dstreg;
signed32 temp;
@@
-4684,6
+4934,7
@@
8.0xfe+8.0x9b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::dmulhu
"dmulhu"
*am33
8.0xfe+8.0x9b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::dmulhu
"dmulhu"
*am33
+*am33_2
{
int imm, dstreg;
signed32 temp;
{
int imm, dstreg;
signed32 temp;
@@
-4704,6
+4955,7
@@
8.0xfe+8.0x0e+4.RN2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5h:::mov
"mov"
*am33
8.0xfe+8.0x0e+4.RN2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5h:::mov
"mov"
*am33
+*am33_2
{
int dstreg;
{
int dstreg;
@@
-4716,6
+4968,7
@@
8.0xfe+8.0x1e+4.RM2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5e:::mov
"mov"
*am33
8.0xfe+8.0x1e+4.RM2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5e:::mov
"mov"
*am33
+*am33_2
{
int srcreg;
{
int srcreg;
@@
-4728,6
+4981,7
@@
8.0xfe+8.0x2e+4.RN2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5i:::movbu
"movbu"
*am33
8.0xfe+8.0x2e+4.RN2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5i:::movbu
"movbu"
*am33
+*am33_2
{
int dstreg;
{
int dstreg;
@@
-4740,6
+4994,7
@@
8.0xfe+8.0x3e+4.RM2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5e:::movbu
"movbu"
*am33
8.0xfe+8.0x3e+4.RM2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5e:::movbu
"movbu"
*am33
+*am33_2
{
int srcreg;
{
int srcreg;
@@
-4752,6
+5007,7
@@
8.0xfe+8.0x4e+4.RN2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5j:::movhu
"movhu"
*am33
8.0xfe+8.0x4e+4.RN2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5j:::movhu
"movhu"
*am33
+*am33_2
{
int dstreg;
{
int dstreg;
@@
-4764,6
+5020,7
@@
8.0xfe+8.0x5e+4.RM2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5e:::movhu
"movhu"
*am33
8.0xfe+8.0x5e+4.RM2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5e:::movhu
"movhu"
*am33
+*am33_2
{
int srcreg;
{
int srcreg;
@@
-4776,6
+5033,7
@@
8.0xf7+8.0x00+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::add_add
"add_add"
*am33
8.0xf7+8.0x00+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::add_add
"add_add"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
@@
-4795,6
+5053,7
@@
8.0xf7+8.0x10+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::add_add
"add_add"
*am33
8.0xf7+8.0x10+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::add_add
"add_add"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
int result1;
{
int srcreg1, dstreg1, dstreg2;
int result1;
@@
-4813,6
+5072,7
@@
8.0xf7+8.0x20+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::add_sub
"add_sub"
*am33
8.0xf7+8.0x20+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::add_sub
"add_sub"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
@@
-4832,6
+5092,7
@@
8.0xf7+8.0x30+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::add_sub
"add_sub"
*am33
8.0xf7+8.0x30+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::add_sub
"add_sub"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
int result1;
{
int srcreg1, dstreg1, dstreg2;
int result1;
@@
-4850,6
+5111,7
@@
8.0xf7+8.0x40+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::add_cmp
"add_cmp"
*am33
8.0xf7+8.0x40+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::add_cmp
"add_cmp"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
{
int srcreg1, srcreg2, dstreg1, dstreg2;
@@
-4867,6
+5129,7
@@
8.0xf7+8.0x50+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::add_cmp
"add_cmp"
*am33
8.0xf7+8.0x50+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::add_cmp
"add_cmp"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
{
int srcreg1, dstreg1, dstreg2;
@@
-4883,6
+5146,7
@@
8.0xf7+8.0x60+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::add_mov
"add_mov"
*am33
8.0xf7+8.0x60+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::add_mov
"add_mov"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
@@
-4902,6
+5166,7
@@
8.0xf7+8.0x70+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::add_mov
"add_mov"
*am33
8.0xf7+8.0x70+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::add_mov
"add_mov"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
int result1;
{
int srcreg1, dstreg1, dstreg2;
int result1;
@@
-4920,6
+5185,7
@@
8.0xf7+8.0x80+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::add_asr
"add_asr"
*am33
8.0xf7+8.0x80+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::add_asr
"add_asr"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
@@
-4942,6
+5208,7
@@
8.0xf7+8.0x90+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::add_asr
"add_asr"
*am33
8.0xf7+8.0x90+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::add_asr
"add_asr"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
int result1;
{
int srcreg1, dstreg1, dstreg2;
int result1;
@@
-4963,6
+5230,7
@@
8.0xf7+8.0xa0+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::add_lsr
"add_lsr"
*am33
8.0xf7+8.0xa0+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::add_lsr
"add_lsr"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
@@
-4982,10
+5250,10
@@
8.0xf7+8.0xb0+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::add_lsr
"add_lsr"
*am33
8.0xf7+8.0xb0+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::add_lsr
"add_lsr"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
int result1;
{
int srcreg1, dstreg1, dstreg2;
int result1;
- signed int temp;
PC = cia;
srcreg1 = translate_rreg (SD_, RM1);
PC = cia;
srcreg1 = translate_rreg (SD_, RM1);
@@
-5002,6
+5270,7
@@
8.0xf7+8.0xc0+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::add_asl
"add_asl"
*am33
8.0xf7+8.0xc0+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::add_asl
"add_asl"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
@@
-5021,10
+5290,10
@@
8.0xf7+8.0xd0+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::add_asl
"add_asl"
*am33
8.0xf7+8.0xd0+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::add_asl
"add_asl"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
int result1;
{
int srcreg1, dstreg1, dstreg2;
int result1;
- signed int temp;
PC = cia;
srcreg1 = translate_rreg (SD_, RM1);
PC = cia;
srcreg1 = translate_rreg (SD_, RM1);
@@
-5040,6
+5309,7
@@
8.0xf7+8.0x01+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::cmp_add
"cmp_add"
*am33
8.0xf7+8.0x01+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::cmp_add
"cmp_add"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
{
int srcreg1, srcreg2, dstreg1, dstreg2;
@@
-5057,6
+5327,7
@@
8.0xf7+8.0x11+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::cmp_add
"cmp_add"
*am33
8.0xf7+8.0x11+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::cmp_add
"cmp_add"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
{
int srcreg1, dstreg1, dstreg2;
@@
-5073,6
+5344,7
@@
8.0xf7+8.0x21+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::cmp_sub
"cmp_sub"
*am33
8.0xf7+8.0x21+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::cmp_sub
"cmp_sub"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
{
int srcreg1, srcreg2, dstreg1, dstreg2;
@@
-5090,6
+5362,7
@@
8.0xf7+8.0x31+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::cmp_sub
"cmp_sub"
*am33
8.0xf7+8.0x31+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::cmp_sub
"cmp_sub"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
{
int srcreg1, dstreg1, dstreg2;
@@
-5106,6
+5379,7
@@
8.0xf7+8.0x61+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::cmp_mov
"cmp_mov"
*am33
8.0xf7+8.0x61+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::cmp_mov
"cmp_mov"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
{
int srcreg1, srcreg2, dstreg1, dstreg2;
@@
-5123,6
+5397,7
@@
8.0xf7+8.0x71+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::cmp_mov
"cmp_mov"
*am33
8.0xf7+8.0x71+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::cmp_mov
"cmp_mov"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
{
int srcreg1, dstreg1, dstreg2;
@@
-5139,6
+5414,7
@@
8.0xf7+8.0x81+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::cmp_asr
"cmp_asr"
*am33
8.0xf7+8.0x81+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::cmp_asr
"cmp_asr"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
signed int temp;
{
int srcreg1, srcreg2, dstreg1, dstreg2;
signed int temp;
@@
-5159,6
+5435,7
@@
8.0xf7+8.0x91+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::cmp_asr
"cmp_asr"
*am33
8.0xf7+8.0x91+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::cmp_asr
"cmp_asr"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
signed int temp;
{
int srcreg1, dstreg1, dstreg2;
signed int temp;
@@
-5178,6
+5455,7
@@
8.0xf7+8.0xa1+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::cmp_lsr
"cmp_lsr"
*am33
8.0xf7+8.0xa1+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::cmp_lsr
"cmp_lsr"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
{
int srcreg1, srcreg2, dstreg1, dstreg2;
@@
-5195,9
+5473,9
@@
8.0xf7+8.0xb1+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::cmp_lsr
"cmp_lsr"
*am33
8.0xf7+8.0xb1+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::cmp_lsr
"cmp_lsr"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
{
int srcreg1, dstreg1, dstreg2;
- signed int temp;
PC = cia;
srcreg1 = translate_rreg (SD_, RM1);
PC = cia;
srcreg1 = translate_rreg (SD_, RM1);
@@
-5213,6
+5491,7
@@
8.0xf7+8.0xc1+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::cmp_asl
"cmp_asl"
*am33
8.0xf7+8.0xc1+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::cmp_asl
"cmp_asl"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
{
int srcreg1, srcreg2, dstreg1, dstreg2;
@@
-5230,9
+5509,9
@@
8.0xf7+8.0xd1+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::cmp_asl
"cmp_asl"
*am33
8.0xf7+8.0xd1+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::cmp_asl
"cmp_asl"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
{
int srcreg1, dstreg1, dstreg2;
- signed int temp;
PC = cia;
srcreg1 = translate_rreg (SD_, RM1);
PC = cia;
srcreg1 = translate_rreg (SD_, RM1);
@@
-5247,6
+5526,7
@@
8.0xf7+8.0x02+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sub_add
"sub_add"
*am33
8.0xf7+8.0x02+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sub_add
"sub_add"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
@@
-5266,6
+5546,7
@@
8.0xf7+8.0x12+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sub_add
"sub_add"
*am33
8.0xf7+8.0x12+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sub_add
"sub_add"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
int result1;
{
int srcreg1, dstreg1, dstreg2;
int result1;
@@
-5284,6
+5565,7
@@
8.0xf7+8.0x22+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sub_sub
"sub_sub"
*am33
8.0xf7+8.0x22+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sub_sub
"sub_sub"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
@@
-5303,6
+5585,7
@@
8.0xf7+8.0x32+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sub_sub
"sub_sub"
*am33
8.0xf7+8.0x32+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sub_sub
"sub_sub"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
int result1;
{
int srcreg1, dstreg1, dstreg2;
int result1;
@@
-5321,6
+5604,7
@@
8.0xf7+8.0x42+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sub_cmp
"sub_cmp"
*am33
8.0xf7+8.0x42+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sub_cmp
"sub_cmp"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
{
int srcreg1, srcreg2, dstreg1, dstreg2;
@@
-5338,9
+5622,9
@@
8.0xf7+8.0x52+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sub_cmp
"sub_cmp"
*am33
8.0xf7+8.0x52+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sub_cmp
"sub_cmp"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
{
int srcreg1, dstreg1, dstreg2;
- int result1;
PC = cia;
srcreg1 = translate_rreg (SD_, RM1);
PC = cia;
srcreg1 = translate_rreg (SD_, RM1);
@@
-5355,6
+5639,7
@@
8.0xf7+8.0x62+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sub_mov
"sub_mov"
*am33
8.0xf7+8.0x62+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sub_mov
"sub_mov"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
@@
-5374,6
+5659,7
@@
8.0xf7+8.0x72+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sub_mov
"sub_mov"
*am33
8.0xf7+8.0x72+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sub_mov
"sub_mov"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
int result1;
{
int srcreg1, dstreg1, dstreg2;
int result1;
@@
-5392,6
+5678,7
@@
8.0xf7+8.0x82+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sub_asr
"sub_asr"
*am33
8.0xf7+8.0x82+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sub_asr
"sub_asr"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
@@
-5414,6
+5701,7
@@
8.0xf7+8.0x92+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sub_asr
"sub_asr"
*am33
8.0xf7+8.0x92+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sub_asr
"sub_asr"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
int result1;
{
int srcreg1, dstreg1, dstreg2;
int result1;
@@
-5435,6
+5723,7
@@
8.0xf7+8.0xa2+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sub_lsr
"sub_lsr"
*am33
8.0xf7+8.0xa2+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sub_lsr
"sub_lsr"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
@@
-5454,10
+5743,10
@@
8.0xf7+8.0xb2+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sub_lsr
"sub_lsr"
*am33
8.0xf7+8.0xb2+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sub_lsr
"sub_lsr"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
int result1;
{
int srcreg1, dstreg1, dstreg2;
int result1;
- signed int temp;
PC = cia;
srcreg1 = translate_rreg (SD_, RM1);
PC = cia;
srcreg1 = translate_rreg (SD_, RM1);
@@
-5474,6
+5763,7
@@
8.0xf7+8.0xc2+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sub_asl
"sub_asl"
*am33
8.0xf7+8.0xc2+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sub_asl
"sub_asl"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
@@
-5493,10
+5783,10
@@
8.0xf7+8.0xd2+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sub_asl
"sub_asl"
*am33
8.0xf7+8.0xd2+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sub_asl
"sub_asl"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
int result1;
{
int srcreg1, dstreg1, dstreg2;
int result1;
- signed int temp;
PC = cia;
srcreg1 = translate_rreg (SD_, RM1);
PC = cia;
srcreg1 = translate_rreg (SD_, RM1);
@@
-5512,6
+5802,7
@@
8.0xf7+8.0x03+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::mov_add
"mov_add"
*am33
8.0xf7+8.0x03+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::mov_add
"mov_add"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
@@
-5531,6
+5822,7
@@
8.0xf7+8.0x13+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::mov_add
"mov_add"
*am33
8.0xf7+8.0x13+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::mov_add
"mov_add"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
int result1;
{
int srcreg1, dstreg1, dstreg2;
int result1;
@@
-5549,6
+5841,7
@@
8.0xf7+8.0x23+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::mov_sub
"mov_sub"
*am33
8.0xf7+8.0x23+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::mov_sub
"mov_sub"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
@@
-5568,6
+5861,7
@@
8.0xf7+8.0x33+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::mov_sub
"mov_sub"
*am33
8.0xf7+8.0x33+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::mov_sub
"mov_sub"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
int result1;
{
int srcreg1, dstreg1, dstreg2;
int result1;
@@
-5586,6
+5880,7
@@
8.0xf7+8.0x43+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::mov_cmp
"mov_cmp"
*am33
8.0xf7+8.0x43+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::mov_cmp
"mov_cmp"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
{
int srcreg1, srcreg2, dstreg1, dstreg2;
@@
-5603,6
+5898,7
@@
8.0xf7+8.0x53+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::mov_cmp
"mov_cmp"
*am33
8.0xf7+8.0x53+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::mov_cmp
"mov_cmp"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
{
int srcreg1, dstreg1, dstreg2;
@@
-5619,6
+5915,7
@@
8.0xf7+8.0x63+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::mov_mov
"mov_mov"
*am33
8.0xf7+8.0x63+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::mov_mov
"mov_mov"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
@@
-5638,6
+5935,7
@@
8.0xf7+8.0x73+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::mov_mov
"mov_mov"
*am33
8.0xf7+8.0x73+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::mov_mov
"mov_mov"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
int result1;
{
int srcreg1, dstreg1, dstreg2;
int result1;
@@
-5656,6
+5954,7
@@
8.0xf7+8.0x83+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::mov_asr
"mov_asr"
*am33
8.0xf7+8.0x83+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::mov_asr
"mov_asr"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
@@
-5678,6
+5977,7
@@
8.0xf7+8.0x93+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::mov_asr
"mov_asr"
*am33
8.0xf7+8.0x93+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::mov_asr
"mov_asr"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
int result1;
{
int srcreg1, dstreg1, dstreg2;
int result1;
@@
-5699,6
+5999,7
@@
8.0xf7+8.0xa3+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::mov_lsr
"mov_lsr"
*am33
8.0xf7+8.0xa3+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::mov_lsr
"mov_lsr"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
@@
-5718,10
+6019,10
@@
8.0xf7+8.0xb3+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::mov_lsr
"mov_lsr"
*am33
8.0xf7+8.0xb3+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::mov_lsr
"mov_lsr"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
int result1;
{
int srcreg1, dstreg1, dstreg2;
int result1;
- signed int temp;
PC = cia;
srcreg1 = translate_rreg (SD_, RM1);
PC = cia;
srcreg1 = translate_rreg (SD_, RM1);
@@
-5738,6
+6039,7
@@
8.0xf7+8.0xc3+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::mov_asl
"mov_asl"
*am33
8.0xf7+8.0xc3+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::mov_asl
"mov_asl"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
@@
-5757,10
+6059,10
@@
8.0xf7+8.0xd3+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::mov_asl
"mov_asl"
*am33
8.0xf7+8.0xd3+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::mov_asl
"mov_asl"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
int result1;
{
int srcreg1, dstreg1, dstreg2;
int result1;
- signed int temp;
PC = cia;
srcreg1 = translate_rreg (SD_, RM1);
PC = cia;
srcreg1 = translate_rreg (SD_, RM1);
@@
-5776,6
+6078,7
@@
8.0xf7+8.0x04+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::add_add
"add_add"
*am33
8.0xf7+8.0x04+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::add_add
"add_add"
*am33
+*am33_2
{
int srcreg2, dstreg1, dstreg2;
int result1;
{
int srcreg2, dstreg1, dstreg2;
int result1;
@@
-5794,6
+6097,7
@@
8.0xf7+8.0x14+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::add_add
"add_add"
*am33
8.0xf7+8.0x14+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::add_add
"add_add"
*am33
+*am33_2
{
int dstreg1, dstreg2;
int result1;
{
int dstreg1, dstreg2;
int result1;
@@
-5811,6
+6115,7
@@
8.0xf7+8.0x24+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::add_sub
"add_sub"
*am33
8.0xf7+8.0x24+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::add_sub
"add_sub"
*am33
+*am33_2
{
int srcreg2, dstreg1, dstreg2;
int result1;
{
int srcreg2, dstreg1, dstreg2;
int result1;
@@
-5829,6
+6134,7
@@
8.0xf7+8.0x34+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::add_sub
"add_sub"
*am33
8.0xf7+8.0x34+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::add_sub
"add_sub"
*am33
+*am33_2
{
int dstreg1, dstreg2;
int result1;
{
int dstreg1, dstreg2;
int result1;
@@
-5846,6
+6152,7
@@
8.0xf7+8.0x44+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::add_cmp
"add_cmp"
*am33
8.0xf7+8.0x44+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::add_cmp
"add_cmp"
*am33
+*am33_2
{
int srcreg2, dstreg1, dstreg2;
{
int srcreg2, dstreg1, dstreg2;
@@
-5862,6
+6169,7
@@
8.0xf7+8.0x54+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::add_cmp
"add_cmp"
*am33
8.0xf7+8.0x54+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::add_cmp
"add_cmp"
*am33
+*am33_2
{
int dstreg1, dstreg2;
{
int dstreg1, dstreg2;
@@
-5877,6
+6185,7
@@
8.0xf7+8.0x64+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::add_mov
"add_mov"
*am33
8.0xf7+8.0x64+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::add_mov
"add_mov"
*am33
+*am33_2
{
int srcreg2, dstreg1, dstreg2;
int result1;
{
int srcreg2, dstreg1, dstreg2;
int result1;
@@
-5895,6
+6204,7
@@
8.0xf7+8.0x74+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::add_mov
"add_mov"
*am33
8.0xf7+8.0x74+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::add_mov
"add_mov"
*am33
+*am33_2
{
int dstreg1, dstreg2;
int result1;
{
int dstreg1, dstreg2;
int result1;
@@
-5912,6
+6222,7
@@
8.0xf7+8.0x84+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::add_asr
"add_asr"
*am33
8.0xf7+8.0x84+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::add_asr
"add_asr"
*am33
+*am33_2
{
int srcreg2, dstreg1, dstreg2;
int result1;
{
int srcreg2, dstreg1, dstreg2;
int result1;
@@
-5933,6
+6244,7
@@
8.0xf7+8.0x94+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::add_asr
"add_asr"
*am33
8.0xf7+8.0x94+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::add_asr
"add_asr"
*am33
+*am33_2
{
int dstreg1, dstreg2;
int result1;
{
int dstreg1, dstreg2;
int result1;
@@
-5953,6
+6265,7
@@
8.0xf7+8.0xa4+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::add_lsr
"add_lsr"
*am33
8.0xf7+8.0xa4+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::add_lsr
"add_lsr"
*am33
+*am33_2
{
int srcreg2, dstreg1, dstreg2;
int result1;
{
int srcreg2, dstreg1, dstreg2;
int result1;
@@
-5971,10
+6284,10
@@
8.0xf7+8.0xb4+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::add_lsr
"add_lsr"
*am33
8.0xf7+8.0xb4+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::add_lsr
"add_lsr"
*am33
+*am33_2
{
int dstreg1, dstreg2;
int result1;
{
int dstreg1, dstreg2;
int result1;
- signed int temp;
PC = cia;
dstreg1 = translate_rreg (SD_, RN1);
PC = cia;
dstreg1 = translate_rreg (SD_, RN1);
@@
-5990,6
+6303,7
@@
8.0xf7+8.0xc4+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::add_asl
"add_asl"
*am33
8.0xf7+8.0xc4+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::add_asl
"add_asl"
*am33
+*am33_2
{
int srcreg2, dstreg1, dstreg2;
int result1;
{
int srcreg2, dstreg1, dstreg2;
int result1;
@@
-6008,10
+6322,10
@@
8.0xf7+8.0xd4+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::add_asl
"add_asl"
*am33
8.0xf7+8.0xd4+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::add_asl
"add_asl"
*am33
+*am33_2
{
int dstreg1, dstreg2;
int result1;
{
int dstreg1, dstreg2;
int result1;
- signed int temp;
PC = cia;
dstreg1 = translate_rreg (SD_, RN1);
PC = cia;
dstreg1 = translate_rreg (SD_, RN1);
@@
-6026,6
+6340,7
@@
8.0xf7+8.0x05+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::cmp_add
"cmp_add"
*am33
8.0xf7+8.0x05+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::cmp_add
"cmp_add"
*am33
+*am33_2
{
int srcreg2, dstreg1, dstreg2;
{
int srcreg2, dstreg1, dstreg2;
@@
-6042,6
+6357,7
@@
8.0xf7+8.0x15+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::cmp_add
"cmp_add"
*am33
8.0xf7+8.0x15+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::cmp_add
"cmp_add"
*am33
+*am33_2
{
int dstreg1, dstreg2;
{
int dstreg1, dstreg2;
@@
-6057,6
+6373,7
@@
8.0xf7+8.0x25+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::cmp_sub
"cmp_sub"
*am33
8.0xf7+8.0x25+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::cmp_sub
"cmp_sub"
*am33
+*am33_2
{
int srcreg2, dstreg1, dstreg2;
{
int srcreg2, dstreg1, dstreg2;
@@
-6073,6
+6390,7
@@
8.0xf7+8.0x35+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::cmp_sub
"cmp_sub"
*am33
8.0xf7+8.0x35+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::cmp_sub
"cmp_sub"
*am33
+*am33_2
{
int dstreg1, dstreg2;
{
int dstreg1, dstreg2;
@@
-6088,6
+6406,7
@@
8.0xf7+8.0x65+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::cmp_mov
"cmp_mov"
*am33
8.0xf7+8.0x65+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::cmp_mov
"cmp_mov"
*am33
+*am33_2
{
int srcreg2, dstreg1, dstreg2;
{
int srcreg2, dstreg1, dstreg2;
@@
-6104,6
+6423,7
@@
8.0xf7+8.0x75+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::cmp_mov
"cmp_mov"
*am33
8.0xf7+8.0x75+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::cmp_mov
"cmp_mov"
*am33
+*am33_2
{
int dstreg1, dstreg2;
{
int dstreg1, dstreg2;
@@
-6119,6
+6439,7
@@
8.0xf7+8.0x85+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::cmp_asr
"cmp_asr"
*am33
8.0xf7+8.0x85+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::cmp_asr
"cmp_asr"
*am33
+*am33_2
{
int srcreg2, dstreg1, dstreg2;
signed int temp;
{
int srcreg2, dstreg1, dstreg2;
signed int temp;
@@
-6138,6
+6459,7
@@
8.0xf7+8.0x95+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::cmp_asr
"cmp_asr"
*am33
8.0xf7+8.0x95+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::cmp_asr
"cmp_asr"
*am33
+*am33_2
{
int dstreg1, dstreg2;
signed int temp;
{
int dstreg1, dstreg2;
signed int temp;
@@
-6156,6
+6478,7
@@
8.0xf7+8.0xa5+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::cmp_lsr
"cmp_lsr"
*am33
8.0xf7+8.0xa5+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::cmp_lsr
"cmp_lsr"
*am33
+*am33_2
{
int srcreg2, dstreg1, dstreg2;
{
int srcreg2, dstreg1, dstreg2;
@@
-6172,9
+6495,9
@@
8.0xf7+8.0xb5+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::cmp_lsr
"cmp_lsr"
*am33
8.0xf7+8.0xb5+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::cmp_lsr
"cmp_lsr"
*am33
+*am33_2
{
int dstreg1, dstreg2;
{
int dstreg1, dstreg2;
- signed int temp;
PC = cia;
dstreg1 = translate_rreg (SD_, RN1);
PC = cia;
dstreg1 = translate_rreg (SD_, RN1);
@@
-6189,6
+6512,7
@@
8.0xf7+8.0xc5+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::cmp_asl
"cmp_asl"
*am33
8.0xf7+8.0xc5+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::cmp_asl
"cmp_asl"
*am33
+*am33_2
{
int srcreg2, dstreg1, dstreg2;
{
int srcreg2, dstreg1, dstreg2;
@@
-6205,9
+6529,9
@@
8.0xf7+8.0xd5+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::cmp_asl
"cmp_asl"
*am33
8.0xf7+8.0xd5+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::cmp_asl
"cmp_asl"
*am33
+*am33_2
{
int dstreg1, dstreg2;
{
int dstreg1, dstreg2;
- signed int temp;
PC = cia;
dstreg1 = translate_rreg (SD_, RN1);
PC = cia;
dstreg1 = translate_rreg (SD_, RN1);
@@
-6221,6
+6545,7
@@
8.0xf7+8.0x06+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::sub_add
"sub_add"
*am33
8.0xf7+8.0x06+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::sub_add
"sub_add"
*am33
+*am33_2
{
int srcreg2, dstreg1, dstreg2;
int result1;
{
int srcreg2, dstreg1, dstreg2;
int result1;
@@
-6239,6
+6564,7
@@
8.0xf7+8.0x16+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::sub_add
"sub_add"
*am33
8.0xf7+8.0x16+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::sub_add
"sub_add"
*am33
+*am33_2
{
int dstreg1, dstreg2;
int result1;
{
int dstreg1, dstreg2;
int result1;
@@
-6256,6
+6582,7
@@
8.0xf7+8.0x26+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::sub_sub
"sub_sub"
*am33
8.0xf7+8.0x26+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::sub_sub
"sub_sub"
*am33
+*am33_2
{
int srcreg2, dstreg1, dstreg2;
int result1;
{
int srcreg2, dstreg1, dstreg2;
int result1;
@@
-6274,6
+6601,7
@@
8.0xf7+8.0x36+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::sub_sub
"sub_sub"
*am33
8.0xf7+8.0x36+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::sub_sub
"sub_sub"
*am33
+*am33_2
{
int dstreg1, dstreg2;
int result1;
{
int dstreg1, dstreg2;
int result1;
@@
-6291,9
+6619,9
@@
8.0xf7+8.0x46+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::sub_cmp
"sub_cmp"
*am33
8.0xf7+8.0x46+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::sub_cmp
"sub_cmp"
*am33
+*am33_2
{
int srcreg2, dstreg1, dstreg2;
{
int srcreg2, dstreg1, dstreg2;
- int result1;
PC = cia;
srcreg2 = translate_rreg (SD_, RM2);
PC = cia;
srcreg2 = translate_rreg (SD_, RM2);
@@
-6308,9
+6636,9
@@
8.0xf7+8.0x56+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::sub_cmp
"sub_cmp"
*am33
8.0xf7+8.0x56+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::sub_cmp
"sub_cmp"
*am33
+*am33_2
{
int dstreg1, dstreg2;
{
int dstreg1, dstreg2;
- int result1;
PC = cia;
dstreg1 = translate_rreg (SD_, RN1);
PC = cia;
dstreg1 = translate_rreg (SD_, RN1);
@@
-6324,6
+6652,7
@@
8.0xf7+8.0x66+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::sub_mov
"sub_mov"
*am33
8.0xf7+8.0x66+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::sub_mov
"sub_mov"
*am33
+*am33_2
{
int srcreg2, dstreg1, dstreg2;
int result1;
{
int srcreg2, dstreg1, dstreg2;
int result1;
@@
-6342,6
+6671,7
@@
8.0xf7+8.0x76+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::sub_mov
"sub_mov"
*am33
8.0xf7+8.0x76+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::sub_mov
"sub_mov"
*am33
+*am33_2
{
int dstreg1, dstreg2;
int result1;
{
int dstreg1, dstreg2;
int result1;
@@
-6359,6
+6689,7
@@
8.0xf7+8.0x86+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::sub_asr
"sub_asr"
*am33
8.0xf7+8.0x86+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::sub_asr
"sub_asr"
*am33
+*am33_2
{
int srcreg2, dstreg1, dstreg2;
int result1;
{
int srcreg2, dstreg1, dstreg2;
int result1;
@@
-6380,6
+6711,7
@@
8.0xf7+8.0x96+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::sub_asr
"sub_asr"
*am33
8.0xf7+8.0x96+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::sub_asr
"sub_asr"
*am33
+*am33_2
{
int dstreg1, dstreg2;
int result1;
{
int dstreg1, dstreg2;
int result1;
@@
-6400,6
+6732,7
@@
8.0xf7+8.0xa6+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::sub_lsr
"sub_lsr"
*am33
8.0xf7+8.0xa6+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::sub_lsr
"sub_lsr"
*am33
+*am33_2
{
int srcreg2, dstreg1, dstreg2;
int result1;
{
int srcreg2, dstreg1, dstreg2;
int result1;
@@
-6418,10
+6751,10
@@
8.0xf7+8.0xb6+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::sub_lsr
"sub_lsr"
*am33
8.0xf7+8.0xb6+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::sub_lsr
"sub_lsr"
*am33
+*am33_2
{
int dstreg1, dstreg2;
int result1;
{
int dstreg1, dstreg2;
int result1;
- signed int temp;
PC = cia;
dstreg1 = translate_rreg (SD_, RN1);
PC = cia;
dstreg1 = translate_rreg (SD_, RN1);
@@
-6437,6
+6770,7
@@
8.0xf7+8.0xc6+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::sub_asl
"sub_asl"
*am33
8.0xf7+8.0xc6+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::sub_asl
"sub_asl"
*am33
+*am33_2
{
int srcreg2, dstreg1, dstreg2;
int result1;
{
int srcreg2, dstreg1, dstreg2;
int result1;
@@
-6455,10
+6789,10
@@
8.0xf7+8.0xd6+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::sub_asl
"sub_asl"
*am33
8.0xf7+8.0xd6+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::sub_asl
"sub_asl"
*am33
+*am33_2
{
int dstreg1, dstreg2;
int result1;
{
int dstreg1, dstreg2;
int result1;
- signed int temp;
PC = cia;
dstreg1 = translate_rreg (SD_, RN1);
PC = cia;
dstreg1 = translate_rreg (SD_, RN1);
@@
-6473,6
+6807,7
@@
8.0xf7+8.0x07+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::mov_add
"mov_add"
*am33
8.0xf7+8.0x07+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::mov_add
"mov_add"
*am33
+*am33_2
{
int srcreg2, dstreg1, dstreg2;
int result1;
{
int srcreg2, dstreg1, dstreg2;
int result1;
@@
-6491,6
+6826,7
@@
8.0xf7+8.0x17+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::mov_add
"mov_add"
*am33
8.0xf7+8.0x17+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::mov_add
"mov_add"
*am33
+*am33_2
{
int dstreg1, dstreg2;
int result1;
{
int dstreg1, dstreg2;
int result1;
@@
-6508,6
+6844,7
@@
8.0xf7+8.0x27+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::mov_sub
"mov_sub"
*am33
8.0xf7+8.0x27+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::mov_sub
"mov_sub"
*am33
+*am33_2
{
int srcreg2, dstreg1, dstreg2;
int result1;
{
int srcreg2, dstreg1, dstreg2;
int result1;
@@
-6526,6
+6863,7
@@
8.0xf7+8.0x37+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::mov_sub
"mov_sub"
*am33
8.0xf7+8.0x37+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::mov_sub
"mov_sub"
*am33
+*am33_2
{
int dstreg1, dstreg2;
int result1;
{
int dstreg1, dstreg2;
int result1;
@@
-6543,6
+6881,7
@@
8.0xf7+8.0x47+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::mov_cmp
"mov_cmp"
*am33
8.0xf7+8.0x47+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::mov_cmp
"mov_cmp"
*am33
+*am33_2
{
int srcreg2, dstreg1, dstreg2;
{
int srcreg2, dstreg1, dstreg2;
@@
-6559,6
+6898,7
@@
8.0xf7+8.0x57+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::mov_cmp
"mov_cmp"
*am33
8.0xf7+8.0x57+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::mov_cmp
"mov_cmp"
*am33
+*am33_2
{
int dstreg1, dstreg2;
{
int dstreg1, dstreg2;
@@
-6574,6
+6914,7
@@
8.0xf7+8.0x67+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::mov_mov
"mov_mov"
*am33
8.0xf7+8.0x67+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::mov_mov
"mov_mov"
*am33
+*am33_2
{
int srcreg2, dstreg1, dstreg2;
int result1;
{
int srcreg2, dstreg1, dstreg2;
int result1;
@@
-6592,6
+6933,7
@@
8.0xf7+8.0x77+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::mov_mov
"mov_mov"
*am33
8.0xf7+8.0x77+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::mov_mov
"mov_mov"
*am33
+*am33_2
{
int dstreg1, dstreg2;
int result1;
{
int dstreg1, dstreg2;
int result1;
@@
-6609,6
+6951,7
@@
8.0xf7+8.0x87+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::mov_asr
"mov_asr"
*am33
8.0xf7+8.0x87+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::mov_asr
"mov_asr"
*am33
+*am33_2
{
int srcreg2, dstreg1, dstreg2;
int result1;
{
int srcreg2, dstreg1, dstreg2;
int result1;
@@
-6630,6
+6973,7
@@
8.0xf7+8.0x97+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::mov_asr
"mov_asr"
*am33
8.0xf7+8.0x97+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::mov_asr
"mov_asr"
*am33
+*am33_2
{
int dstreg1, dstreg2;
int result1;
{
int dstreg1, dstreg2;
int result1;
@@
-6650,6
+6994,7
@@
8.0xf7+8.0xa7+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::mov_lsr
"mov_lsr"
*am33
8.0xf7+8.0xa7+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::mov_lsr
"mov_lsr"
*am33
+*am33_2
{
int srcreg2, dstreg1, dstreg2;
int result1;
{
int srcreg2, dstreg1, dstreg2;
int result1;
@@
-6668,10
+7013,10
@@
8.0xf7+8.0xb7+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::mov_lsr
"mov_lsr"
*am33
8.0xf7+8.0xb7+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::mov_lsr
"mov_lsr"
*am33
+*am33_2
{
int dstreg1, dstreg2;
int result1;
{
int dstreg1, dstreg2;
int result1;
- signed int temp;
PC = cia;
dstreg1 = translate_rreg (SD_, RN1);
PC = cia;
dstreg1 = translate_rreg (SD_, RN1);
@@
-6687,6
+7032,7
@@
8.0xf7+8.0xc7+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::mov_asl
"mov_asl"
*am33
8.0xf7+8.0xc7+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::mov_asl
"mov_asl"
*am33
+*am33_2
{
int srcreg2, dstreg1, dstreg2;
int result1;
{
int srcreg2, dstreg1, dstreg2;
int result1;
@@
-6705,10
+7051,10
@@
8.0xf7+8.0xd7+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::mov_asl
"mov_asl"
*am33
8.0xf7+8.0xd7+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::mov_asl
"mov_asl"
*am33
+*am33_2
{
int dstreg1, dstreg2;
int result1;
{
int dstreg1, dstreg2;
int result1;
- signed int temp;
PC = cia;
dstreg1 = translate_rreg (SD_, RN1);
PC = cia;
dstreg1 = translate_rreg (SD_, RN1);
@@
-6723,6
+7069,7
@@
8.0xf7+8.0x08+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::and_add
"and_add"
*am33
8.0xf7+8.0x08+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::and_add
"and_add"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
@@
-6742,6
+7089,7
@@
8.0xf7+8.0x18+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::and_add
"and_add"
*am33
8.0xf7+8.0x18+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::and_add
"and_add"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
int result1;
{
int srcreg1, dstreg1, dstreg2;
int result1;
@@
-6760,6
+7108,7
@@
8.0xf7+8.0x28+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::and_sub
"and_sub"
*am33
8.0xf7+8.0x28+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::and_sub
"and_sub"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
@@
-6779,6
+7128,7
@@
8.0xf7+8.0x38+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::and_sub
"and_sub"
*am33
8.0xf7+8.0x38+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::and_sub
"and_sub"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
int result1;
{
int srcreg1, dstreg1, dstreg2;
int result1;
@@
-6797,6
+7147,7
@@
8.0xf7+8.0x48+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::and_cmp
"and_cmp"
*am33
8.0xf7+8.0x48+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::and_cmp
"and_cmp"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
{
int srcreg1, srcreg2, dstreg1, dstreg2;
@@
-6814,6
+7165,7
@@
8.0xf7+8.0x58+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::and_cmp
"and_cmp"
*am33
8.0xf7+8.0x58+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::and_cmp
"and_cmp"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
{
int srcreg1, dstreg1, dstreg2;
@@
-6830,6
+7182,7
@@
8.0xf7+8.0x68+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::and_mov
"and_mov"
*am33
8.0xf7+8.0x68+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::and_mov
"and_mov"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
@@
-6849,6
+7202,7
@@
8.0xf7+8.0x78+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::and_mov
"and_mov"
*am33
8.0xf7+8.0x78+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::and_mov
"and_mov"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
int result1;
{
int srcreg1, dstreg1, dstreg2;
int result1;
@@
-6867,6
+7221,7
@@
8.0xf7+8.0x88+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::and_asr
"and_asr"
*am33
8.0xf7+8.0x88+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::and_asr
"and_asr"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
@@
-6889,6
+7244,7
@@
8.0xf7+8.0x98+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::and_asr
"and_asr"
*am33
8.0xf7+8.0x98+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::and_asr
"and_asr"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
int result1;
{
int srcreg1, dstreg1, dstreg2;
int result1;
@@
-6910,6
+7266,7
@@
8.0xf7+8.0xa8+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::and_lsr
"and_lsr"
*am33
8.0xf7+8.0xa8+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::and_lsr
"and_lsr"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
@@
-6929,10
+7286,10
@@
8.0xf7+8.0xb8+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::and_lsr
"and_lsr"
*am33
8.0xf7+8.0xb8+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::and_lsr
"and_lsr"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
int result1;
{
int srcreg1, dstreg1, dstreg2;
int result1;
- signed int temp;
PC = cia;
srcreg1 = translate_rreg (SD_, RM1);
PC = cia;
srcreg1 = translate_rreg (SD_, RM1);
@@
-6949,6
+7306,7
@@
8.0xf7+8.0xc8+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::and_asl
"and_asl"
*am33
8.0xf7+8.0xc8+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::and_asl
"and_asl"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
@@
-6968,10
+7326,10
@@
8.0xf7+8.0xd8+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::and_asl
"and_asl"
*am33
8.0xf7+8.0xd8+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::and_asl
"and_asl"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
int result1;
{
int srcreg1, dstreg1, dstreg2;
int result1;
- signed int temp;
PC = cia;
srcreg1 = translate_rreg (SD_, RM1);
PC = cia;
srcreg1 = translate_rreg (SD_, RM1);
@@
-6987,6
+7345,7
@@
8.0xf7+8.0x09+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::dmach_add
"dmach_add"
*am33
8.0xf7+8.0x09+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::dmach_add
"dmach_add"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
signed32 temp, temp2, sum;
{
int srcreg1, srcreg2, dstreg1, dstreg2;
signed32 temp, temp2, sum;
@@
-7011,6
+7370,7
@@
8.0xf7+8.0x19+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::dmach_add
"dmach_add"
*am33
8.0xf7+8.0x19+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::dmach_add
"dmach_add"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
signed32 temp, temp2, sum;
{
int srcreg1, dstreg1, dstreg2;
signed32 temp, temp2, sum;
@@
-7034,6
+7394,7
@@
8.0xf7+8.0x29+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::dmach_sub
"dmach_sub"
*am33
8.0xf7+8.0x29+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::dmach_sub
"dmach_sub"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
signed32 temp, temp2, sum;
{
int srcreg1, srcreg2, dstreg1, dstreg2;
signed32 temp, temp2, sum;
@@
-7058,6
+7419,7
@@
8.0xf7+8.0x39+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::dmach_sub
"dmach_sub"
*am33
8.0xf7+8.0x39+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::dmach_sub
"dmach_sub"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
signed32 temp, temp2, sum;
{
int srcreg1, dstreg1, dstreg2;
signed32 temp, temp2, sum;
@@
-7081,6
+7443,7
@@
8.0xf7+8.0x49+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::dmach_cmp
"dmach_cmp"
*am33
8.0xf7+8.0x49+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::dmach_cmp
"dmach_cmp"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
signed32 temp, temp2, sum;
{
int srcreg1, srcreg2, dstreg1, dstreg2;
signed32 temp, temp2, sum;
@@
-7105,6
+7468,7
@@
8.0xf7+8.0x59+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::dmach_cmp
"dmach_cmp"
*am33
8.0xf7+8.0x59+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::dmach_cmp
"dmach_cmp"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
signed32 temp, temp2, sum;
{
int srcreg1, dstreg1, dstreg2;
signed32 temp, temp2, sum;
@@
-7128,6
+7492,7
@@
8.0xf7+8.0x69+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::dmach_mov
"dmach_mov"
*am33
8.0xf7+8.0x69+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::dmach_mov
"dmach_mov"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
signed32 temp, temp2, sum;
{
int srcreg1, srcreg2, dstreg1, dstreg2;
signed32 temp, temp2, sum;
@@
-7152,6
+7517,7
@@
8.0xf7+8.0x79+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::dmach_mov
"dmach_mov"
*am33
8.0xf7+8.0x79+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::dmach_mov
"dmach_mov"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
signed32 temp, temp2, sum;
{
int srcreg1, dstreg1, dstreg2;
signed32 temp, temp2, sum;
@@
-7175,6
+7541,7
@@
8.0xf7+8.0x89+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::dmach_asr
"dmach_asr"
*am33
8.0xf7+8.0x89+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::dmach_asr
"dmach_asr"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
signed32 temp, temp2, sum;
{
int srcreg1, srcreg2, dstreg1, dstreg2;
signed32 temp, temp2, sum;
@@
-7201,6
+7568,7
@@
8.0xf7+8.0x99+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::dmach_asr
"dmach_asr"
*am33
8.0xf7+8.0x99+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::dmach_asr
"dmach_asr"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
signed32 temp, temp2, sum;
{
int srcreg1, dstreg1, dstreg2;
signed32 temp, temp2, sum;
@@
-7226,6
+7594,7
@@
8.0xf7+8.0xa9+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::dmach_lsr
"dmach_lsr"
*am33
8.0xf7+8.0xa9+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::dmach_lsr
"dmach_lsr"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
signed32 temp, temp2, sum;
{
int srcreg1, srcreg2, dstreg1, dstreg2;
signed32 temp, temp2, sum;
@@
-7250,6
+7619,7
@@
8.0xf7+8.0xb9+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::dmach_lsr
"dmach_lsr"
*am33
8.0xf7+8.0xb9+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::dmach_lsr
"dmach_lsr"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
signed32 temp, temp2, sum;
{
int srcreg1, dstreg1, dstreg2;
signed32 temp, temp2, sum;
@@
-7274,6
+7644,7
@@
8.0xf7+8.0xc9+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::dmach_asl
"dmach_asl"
*am33
8.0xf7+8.0xc9+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::dmach_asl
"dmach_asl"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
signed32 temp, temp2, sum;
{
int srcreg1, srcreg2, dstreg1, dstreg2;
signed32 temp, temp2, sum;
@@
-7298,6
+7669,7
@@
8.0xf7+8.0xd9+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::dmach_asl
"dmach_asl"
*am33
8.0xf7+8.0xd9+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::dmach_asl
"dmach_asl"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
signed32 temp, temp2, sum;
{
int srcreg1, dstreg1, dstreg2;
signed32 temp, temp2, sum;
@@
-7321,6
+7693,7
@@
8.0xf7+8.0x0a+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::xor_add
"xor_add"
*am33
8.0xf7+8.0x0a+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::xor_add
"xor_add"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
@@
-7340,6
+7713,7
@@
8.0xf7+8.0x1a+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::xor_add
"xor_add"
*am33
8.0xf7+8.0x1a+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::xor_add
"xor_add"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
int result1;
{
int srcreg1, dstreg1, dstreg2;
int result1;
@@
-7358,6
+7732,7
@@
8.0xf7+8.0x2a+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::xor_sub
"xor_sub"
*am33
8.0xf7+8.0x2a+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::xor_sub
"xor_sub"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
@@
-7377,6
+7752,7
@@
8.0xf7+8.0x3a+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::xor_sub
"xor_sub"
*am33
8.0xf7+8.0x3a+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::xor_sub
"xor_sub"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
int result1;
{
int srcreg1, dstreg1, dstreg2;
int result1;
@@
-7395,6
+7771,7
@@
8.0xf7+8.0x4a+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::xor_cmp
"xor_cmp"
*am33
8.0xf7+8.0x4a+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::xor_cmp
"xor_cmp"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
{
int srcreg1, srcreg2, dstreg1, dstreg2;
@@
-7412,6
+7789,7
@@
8.0xf7+8.0x5a+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::xor_cmp
"xor_cmp"
*am33
8.0xf7+8.0x5a+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::xor_cmp
"xor_cmp"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
{
int srcreg1, dstreg1, dstreg2;
@@
-7428,6
+7806,7
@@
8.0xf7+8.0x6a+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::xor_mov
"xor_mov"
*am33
8.0xf7+8.0x6a+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::xor_mov
"xor_mov"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
@@
-7447,6
+7826,7
@@
8.0xf7+8.0x7a+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::xor_mov
"xor_mov"
*am33
8.0xf7+8.0x7a+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::xor_mov
"xor_mov"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
int result1;
{
int srcreg1, dstreg1, dstreg2;
int result1;
@@
-7465,6
+7845,7
@@
8.0xf7+8.0x8a+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::xor_asr
"xor_asr"
*am33
8.0xf7+8.0x8a+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::xor_asr
"xor_asr"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
@@
-7487,6
+7868,7
@@
8.0xf7+8.0x9a+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::xor_asr
"xor_asr"
*am33
8.0xf7+8.0x9a+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::xor_asr
"xor_asr"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
int result1;
{
int srcreg1, dstreg1, dstreg2;
int result1;
@@
-7508,6
+7890,7
@@
8.0xf7+8.0xaa+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::xor_lsr
"xor_lsr"
*am33
8.0xf7+8.0xaa+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::xor_lsr
"xor_lsr"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
@@
-7527,10
+7910,10
@@
8.0xf7+8.0xba+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::xor_lsr
"xor_lsr"
*am33
8.0xf7+8.0xba+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::xor_lsr
"xor_lsr"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
int result1;
{
int srcreg1, dstreg1, dstreg2;
int result1;
- signed int temp;
PC = cia;
srcreg1 = translate_rreg (SD_, RM1);
PC = cia;
srcreg1 = translate_rreg (SD_, RM1);
@@
-7547,6
+7930,7
@@
8.0xf7+8.0xca+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::xor_asl
"xor_asl"
*am33
8.0xf7+8.0xca+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::xor_asl
"xor_asl"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
@@
-7566,10
+7950,10
@@
8.0xf7+8.0xda+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::xor_asl
"xor_asl"
*am33
8.0xf7+8.0xda+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::xor_asl
"xor_asl"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
int result1;
{
int srcreg1, dstreg1, dstreg2;
int result1;
- signed int temp;
PC = cia;
srcreg1 = translate_rreg (SD_, RM1);
PC = cia;
srcreg1 = translate_rreg (SD_, RM1);
@@
-7585,6
+7969,7
@@
8.0xf7+8.0x0b+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::swhw_add
"swhw_add"
*am33
8.0xf7+8.0x0b+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::swhw_add
"swhw_add"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
@@
-7604,6
+7989,7
@@
8.0xf7+8.0x1b+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::swhw_add
"swhw_add"
*am33
8.0xf7+8.0x1b+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::swhw_add
"swhw_add"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
int result1;
{
int srcreg1, dstreg1, dstreg2;
int result1;
@@
-7623,6
+8009,7
@@
8.0xf7+8.0x2b+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::swhw_sub
"swhw_sub"
*am33
8.0xf7+8.0x2b+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::swhw_sub
"swhw_sub"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
@@
-7643,6
+8030,7
@@
8.0xf7+8.0x3b+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::swhw_sub
"swhw_sub"
*am33
8.0xf7+8.0x3b+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::swhw_sub
"swhw_sub"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
int result1;
{
int srcreg1, dstreg1, dstreg2;
int result1;
@@
-7662,6
+8050,7
@@
8.0xf7+8.0x4b+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::swhw_cmp
"swhw_cmp"
*am33
8.0xf7+8.0x4b+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::swhw_cmp
"swhw_cmp"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
{
int srcreg1, srcreg2, dstreg1, dstreg2;
@@
-7680,6
+8069,7
@@
8.0xf7+8.0x5b+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::swhw_cmp
"swhw_cmp"
*am33
8.0xf7+8.0x5b+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::swhw_cmp
"swhw_cmp"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
{
int srcreg1, dstreg1, dstreg2;
@@
-7697,6
+8087,7
@@
8.0xf7+8.0x6b+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::swhw_mov
"swhw_mov"
*am33
8.0xf7+8.0x6b+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::swhw_mov
"swhw_mov"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
@@
-7717,6
+8108,7
@@
8.0xf7+8.0x7b+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::swhw_mov
"swhw_mov"
*am33
8.0xf7+8.0x7b+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::swhw_mov
"swhw_mov"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
int result1;
{
int srcreg1, dstreg1, dstreg2;
int result1;
@@
-7736,6
+8128,7
@@
8.0xf7+8.0x8b+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::swhw_asr
"swhw_asr"
*am33
8.0xf7+8.0x8b+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::swhw_asr
"swhw_asr"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
@@
-7759,6
+8152,7
@@
8.0xf7+8.0x9b+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::swhw_asr
"swhw_asr"
*am33
8.0xf7+8.0x9b+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::swhw_asr
"swhw_asr"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
int result1;
{
int srcreg1, dstreg1, dstreg2;
int result1;
@@
-7781,6
+8175,7
@@
8.0xf7+8.0xab+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::swhw_lsr
"swhw_lsr"
*am33
8.0xf7+8.0xab+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::swhw_lsr
"swhw_lsr"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
@@
-7801,10
+8196,10
@@
8.0xf7+8.0xbb+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::swhw_lsr
"swhw_lsr"
*am33
8.0xf7+8.0xbb+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::swhw_lsr
"swhw_lsr"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
int result1;
{
int srcreg1, dstreg1, dstreg2;
int result1;
- signed int temp;
PC = cia;
srcreg1 = translate_rreg (SD_, RM1);
PC = cia;
srcreg1 = translate_rreg (SD_, RM1);
@@
-7822,6
+8217,7
@@
8.0xf7+8.0xcb+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::swhw_asl
"swhw_asl"
*am33
8.0xf7+8.0xcb+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::swhw_asl
"swhw_asl"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
@@
-7842,10
+8238,10
@@
8.0xf7+8.0xdb+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::swhw_asl
"swhw_asl"
*am33
8.0xf7+8.0xdb+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::swhw_asl
"swhw_asl"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
int result1;
{
int srcreg1, dstreg1, dstreg2;
int result1;
- signed int temp;
PC = cia;
srcreg1 = translate_rreg (SD_, RM1);
PC = cia;
srcreg1 = translate_rreg (SD_, RM1);
@@
-7862,6
+8258,7
@@
8.0xf7+8.0x0c+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::or_add
"or_add"
*am33
8.0xf7+8.0x0c+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::or_add
"or_add"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
@@
-7881,6
+8278,7
@@
8.0xf7+8.0x1c+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::or_add
"or_add"
*am33
8.0xf7+8.0x1c+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::or_add
"or_add"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
int result1;
{
int srcreg1, dstreg1, dstreg2;
int result1;
@@
-7899,6
+8297,7
@@
8.0xf7+8.0x2c+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::or_sub
"or_sub"
*am33
8.0xf7+8.0x2c+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::or_sub
"or_sub"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
@@
-7918,6
+8317,7
@@
8.0xf7+8.0x3c+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::or_sub
"or_sub"
*am33
8.0xf7+8.0x3c+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::or_sub
"or_sub"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
int result1;
{
int srcreg1, dstreg1, dstreg2;
int result1;
@@
-7936,6
+8336,7
@@
8.0xf7+8.0x4c+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::or_cmp
"or_cmp"
*am33
8.0xf7+8.0x4c+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::or_cmp
"or_cmp"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
{
int srcreg1, srcreg2, dstreg1, dstreg2;
@@
-7953,6
+8354,7
@@
8.0xf7+8.0x5c+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::or_cmp
"or_cmp"
*am33
8.0xf7+8.0x5c+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::or_cmp
"or_cmp"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
{
int srcreg1, dstreg1, dstreg2;
@@
-7969,6
+8371,7
@@
8.0xf7+8.0x6c+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::or_mov
"or_mov"
*am33
8.0xf7+8.0x6c+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::or_mov
"or_mov"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
@@
-7988,6
+8391,7
@@
8.0xf7+8.0x7c+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::or_mov
"or_mov"
*am33
8.0xf7+8.0x7c+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::or_mov
"or_mov"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
int result1;
{
int srcreg1, dstreg1, dstreg2;
int result1;
@@
-8006,6
+8410,7
@@
8.0xf7+8.0x8c+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::or_asr
"or_asr"
*am33
8.0xf7+8.0x8c+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::or_asr
"or_asr"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
@@
-8028,6
+8433,7
@@
8.0xf7+8.0x9c+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::or_asr
"or_asr"
*am33
8.0xf7+8.0x9c+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::or_asr
"or_asr"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
int result1;
{
int srcreg1, dstreg1, dstreg2;
int result1;
@@
-8049,6
+8455,7
@@
8.0xf7+8.0xac+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::or_lsr
"or_lsr"
*am33
8.0xf7+8.0xac+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::or_lsr
"or_lsr"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
@@
-8068,10
+8475,10
@@
8.0xf7+8.0xbc+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::or_lsr
"or_lsr"
*am33
8.0xf7+8.0xbc+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::or_lsr
"or_lsr"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
int result1;
{
int srcreg1, dstreg1, dstreg2;
int result1;
- signed int temp;
PC = cia;
srcreg1 = translate_rreg (SD_, RM1);
PC = cia;
srcreg1 = translate_rreg (SD_, RM1);
@@
-8088,6
+8495,7
@@
8.0xf7+8.0xcc+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::or_asl
"or_asl"
*am33
8.0xf7+8.0xcc+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::or_asl
"or_asl"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
@@
-8107,10
+8515,10
@@
8.0xf7+8.0xdc+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::or_asl
"or_asl"
*am33
8.0xf7+8.0xdc+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::or_asl
"or_asl"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
int result1;
{
int srcreg1, dstreg1, dstreg2;
int result1;
- signed int temp;
PC = cia;
srcreg1 = translate_rreg (SD_, RM1);
PC = cia;
srcreg1 = translate_rreg (SD_, RM1);
@@
-8126,6
+8534,7
@@
8.0xf7+8.0x0d+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sat16_add
"sat16_add"
*am33
8.0xf7+8.0x0d+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sat16_add
"sat16_add"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
@@
-8151,6
+8560,7
@@
8.0xf7+8.0x1d+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sat16_add
"sat16_add"
*am33
8.0xf7+8.0x1d+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sat16_add
"sat16_add"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
int result1;
{
int srcreg1, dstreg1, dstreg2;
int result1;
@@
-8175,6
+8585,7
@@
8.0xf7+8.0x2d+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sat16_sub
"sat16_sub"
*am33
8.0xf7+8.0x2d+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sat16_sub
"sat16_sub"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
@@
-8200,6
+8611,7
@@
8.0xf7+8.0x3d+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sat16_sub
"sat16_sub"
*am33
8.0xf7+8.0x3d+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sat16_sub
"sat16_sub"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
int result1;
{
int srcreg1, dstreg1, dstreg2;
int result1;
@@
-8224,9
+8636,9
@@
8.0xf7+8.0x4d+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sat16_cmp
"sat16_cmp"
*am33
8.0xf7+8.0x4d+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sat16_cmp
"sat16_cmp"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
{
int srcreg1, srcreg2, dstreg1, dstreg2;
- int result1;
PC = cia;
srcreg1 = translate_rreg (SD_, RM1);
PC = cia;
srcreg1 = translate_rreg (SD_, RM1);
@@
-8234,7
+8646,7
@@
dstreg1 = translate_rreg (SD_, RN1);
dstreg2 = translate_rreg (SD_, RN2);
dstreg1 = translate_rreg (SD_, RN1);
dstreg2 = translate_rreg (SD_, RN2);
-
State.regs[dstreg1] = result1
;
+
genericCmp (State.regs[dstreg2], State.regs[dstreg1])
;
if (State.regs[srcreg1] >= 0x7fff)
State.regs[dstreg1] = 0x7fff;
else if (State.regs[srcreg1] <= 0xffff8000)
if (State.regs[srcreg1] >= 0x7fff)
State.regs[dstreg1] = 0x7fff;
else if (State.regs[srcreg1] <= 0xffff8000)
@@
-8247,6
+8659,7
@@
8.0xf7+8.0x5d+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sat16_cmp
"sat16_cmp"
*am33
8.0xf7+8.0x5d+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sat16_cmp
"sat16_cmp"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
{
int srcreg1, dstreg1, dstreg2;
@@
-8268,6
+8681,7
@@
8.0xf7+8.0x6d+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sat16_mov
"sat16_mov"
*am33
8.0xf7+8.0x6d+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sat16_mov
"sat16_mov"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
@@
-8293,6
+8707,7
@@
8.0xf7+8.0x7d+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sat16_mov
"sat16_mov"
*am33
8.0xf7+8.0x7d+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sat16_mov
"sat16_mov"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
int result1;
{
int srcreg1, dstreg1, dstreg2;
int result1;
@@
-8317,6
+8732,7
@@
8.0xf7+8.0x8d+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sat16_asr
"sat16_asr"
*am33
8.0xf7+8.0x8d+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sat16_asr
"sat16_asr"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
@@
-8345,6
+8761,7
@@
8.0xf7+8.0x9d+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sat16_asr
"sat16_asr"
*am33
8.0xf7+8.0x9d+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sat16_asr
"sat16_asr"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
int result1;
{
int srcreg1, dstreg1, dstreg2;
int result1;
@@
-8372,6
+8789,7
@@
8.0xf7+8.0xad+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sat16_lsr
"sat16_lsr"
*am33
8.0xf7+8.0xad+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sat16_lsr
"sat16_lsr"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
@@
-8397,10
+8815,10
@@
8.0xf7+8.0xbd+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sat16_lsr
"sat16_lsr"
*am33
8.0xf7+8.0xbd+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sat16_lsr
"sat16_lsr"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
int result1;
{
int srcreg1, dstreg1, dstreg2;
int result1;
- signed int temp;
PC = cia;
srcreg1 = translate_rreg (SD_, RM1);
PC = cia;
srcreg1 = translate_rreg (SD_, RM1);
@@
-8423,6
+8841,7
@@
8.0xf7+8.0xcd+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sat16_asl
"sat16_asl"
*am33
8.0xf7+8.0xcd+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sat16_asl
"sat16_asl"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
@@
-8448,10
+8867,10
@@
8.0xf7+8.0xdd+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sat16_asl
"sat16_asl"
*am33
8.0xf7+8.0xdd+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sat16_asl
"sat16_asl"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
int result1;
{
int srcreg1, dstreg1, dstreg2;
int result1;
- signed int temp;
PC = cia;
srcreg1 = translate_rreg (SD_, RM1);
PC = cia;
srcreg1 = translate_rreg (SD_, RM1);
@@
-8473,9
+8892,9
@@
8.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0x0:D2:::mov_llt
"mov_llt"
*am33
8.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0x0:D2:::mov_llt
"mov_llt"
*am33
+*am33_2
{
int srcreg, dstreg;
{
int srcreg, dstreg;
- int result1;
PC = cia;
srcreg = translate_rreg (SD_, RM);
PC = cia;
srcreg = translate_rreg (SD_, RM);
@@
-8489,13
+8908,13
@@
State.regs[REG_PC] = State.regs[REG_LAR] - 4;
nia = PC;
}
State.regs[REG_PC] = State.regs[REG_LAR] - 4;
nia = PC;
}
- State.regs[dstreg] = result1;
}
// 1111 0111 1110 0000 Rm1 Rn1 imm4 0001; mov_lgt (Rm+,imm4),Rn
8.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0x1:D2:::mov_lgt
"mov_lgt"
*am33
}
// 1111 0111 1110 0000 Rm1 Rn1 imm4 0001; mov_lgt (Rm+,imm4),Rn
8.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0x1:D2:::mov_lgt
"mov_lgt"
*am33
+*am33_2
{
int srcreg, dstreg;
{
int srcreg, dstreg;
@@
-8518,6
+8937,7
@@
8.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0x2:D2:::mov_lge
"mov_lge"
*am33
8.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0x2:D2:::mov_lge
"mov_lge"
*am33
+*am33_2
{
int srcreg, dstreg;
{
int srcreg, dstreg;
@@
-8539,6
+8959,7
@@
8.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0x3:D2:::mov_lle
"mov_lle"
*am33
8.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0x3:D2:::mov_lle
"mov_lle"
*am33
+*am33_2
{
int srcreg, dstreg;
{
int srcreg, dstreg;
@@
-8561,6
+8982,7
@@
8.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0x4:D2:::mov_lcs
"mov_lcs"
*am33
8.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0x4:D2:::mov_lcs
"mov_lcs"
*am33
+*am33_2
{
int srcreg, dstreg;
{
int srcreg, dstreg;
@@
-8582,6
+9004,7
@@
8.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0x5:D2:::mov_lhi
"mov_lhi"
*am33
8.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0x5:D2:::mov_lhi
"mov_lhi"
*am33
+*am33_2
{
int srcreg, dstreg;
{
int srcreg, dstreg;
@@
-8603,6
+9026,7
@@
8.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0x6:D2:::mov_lcc
"mov_lcc"
*am33
8.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0x6:D2:::mov_lcc
"mov_lcc"
*am33
+*am33_2
{
int srcreg, dstreg;
{
int srcreg, dstreg;
@@
-8624,6
+9048,7
@@
8.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0x7:D2:::mov_lls
"mov_lls"
*am33
8.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0x7:D2:::mov_lls
"mov_lls"
*am33
+*am33_2
{
int srcreg, dstreg;
{
int srcreg, dstreg;
@@
-8645,6
+9070,7
@@
8.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0x8:D2:::mov_leq
"mov_leq"
*am33
8.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0x8:D2:::mov_leq
"mov_leq"
*am33
+*am33_2
{
int srcreg, dstreg;
{
int srcreg, dstreg;
@@
-8666,6
+9092,7
@@
8.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0x9:D2:::mov_lne
"mov_lne"
*am33
8.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0x9:D2:::mov_lne
"mov_lne"
*am33
+*am33_2
{
int srcreg, dstreg;
{
int srcreg, dstreg;
@@
-8687,6
+9114,7
@@
8.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0xa:D2:::mov_lra
"mov_lra"
*am33
8.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0xa:D2:::mov_lra
"mov_lra"
*am33
+*am33_2
{
int srcreg, dstreg;
{
int srcreg, dstreg;
@@
-8701,3
+9129,4
@@
nia = PC;
}
nia = PC;
}
+:include::am33_2:am33-2.igen
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