+ temp = ((signed32)(signed16)(State.regs[dstreg] & 0xffff)
+ * (signed32)(signed16)(imm & 0xffff));
+ State.regs[REG_MDRQ] = temp;
+ temp = ((signed32)(signed16)((State.regs[dstreg] >> 16) & 0xffff)
+ * (signed32)(signed16)((imm>>16) & 0xffff));
+ State.regs[dstreg] = temp;
+}
+
+// 1111 1110 1001 1011 Rn Rn IMM32; dmulhu imm32,Rn
+8.0xfe+8.0x9b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::dmulhu
+"dmulhu"
+*am33
+*am33_2
+{
+ int imm, dstreg;
+ signed32 temp;
+
+ PC = cia;
+ dstreg = translate_rreg (SD_, RN0);
+ imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
+
+ temp = ((unsigned32)(State.regs[dstreg] & 0xffff)
+ * (unsigned32)(imm & 0xffff));
+ State.regs[REG_MDRQ] = temp;
+ temp = ((unsigned32)((State.regs[dstreg] >> 16) & 0xffff)
+ * (unsigned32)((imm >>16) & 0xffff));
+ State.regs[dstreg] = temp;
+}
+
+// 1111 1110 0000 1110 Rn 0000 IMM32; mov (abs32),Rn
+8.0xfe+8.0x0e+4.RN2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5h:::mov
+"mov"
+*am33
+*am33_2
+{
+ int dstreg;
+
+ PC = cia;
+ dstreg = translate_rreg (SD_, RN2);
+ State.regs[dstreg] = load_word (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
+}
+
+// 1111 1110 0001 1110 Rm 0000 IMM32; mov Rn,(abs32)
+8.0xfe+8.0x1e+4.RM2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5e:::mov
+"mov"
+*am33
+*am33_2
+{
+ int srcreg;
+
+ PC = cia;
+ srcreg = translate_rreg (SD_, RM2);
+ store_word (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D), State.regs[srcreg]);
+}
+
+// 1111 1110 0020 1110 Rn 0000 IMM32; movbu (abs32),Rn
+8.0xfe+8.0x2e+4.RN2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5i:::movbu
+"movbu"
+*am33
+*am33_2
+{
+ int dstreg;
+
+ PC = cia;
+ dstreg = translate_rreg (SD_, RN2);
+ State.regs[dstreg] = load_byte (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
+}
+
+// 1111 1110 0011 1110 Rm 0000 IMM32; movbu Rn,(abs32)
+8.0xfe+8.0x3e+4.RM2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5e:::movbu
+"movbu"
+*am33
+*am33_2
+{
+ int srcreg;
+
+ PC = cia;
+ srcreg = translate_rreg (SD_, RM2);
+ store_byte (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D), State.regs[srcreg]);
+}
+
+// 1111 1110 0100 1110 Rn 0000 IMM32; movhu (abs32),Rn
+8.0xfe+8.0x4e+4.RN2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5j:::movhu
+"movhu"
+*am33
+*am33_2
+{
+ int dstreg;
+
+ PC = cia;
+ dstreg = translate_rreg (SD_, RN2);
+ State.regs[dstreg] = load_half (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
+}
+
+// 1111 1110 0101 1110 Rm 0000 IMM32; movhu Rn,(abs32)
+8.0xfe+8.0x5e+4.RM2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5e:::movhu
+"movhu"
+*am33
+*am33_2
+{
+ int srcreg;
+
+ PC = cia;
+ srcreg = translate_rreg (SD_, RM2);
+ store_half (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D), State.regs[srcreg]);
+}
+
+// 1111 0111 0000 0000 Rm1 Rn1 Rm2 Rn2; add_add Rm1, Rn1, Rm2, Rn2
+8.0xf7+8.0x00+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::add_add
+"add_add"
+*am33
+*am33_2
+{
+ int srcreg1, srcreg2, dstreg1, dstreg2;
+ int result1;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ srcreg2 = translate_rreg (SD_, RM2);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ result1 = State.regs[dstreg1] + State.regs[srcreg1];
+ State.regs[dstreg2] += State.regs[srcreg2];
+ State.regs[dstreg1] = result1;
+}
+
+// 1111 0111 0001 0000 Rm1 Rn1 imm4 Rn2; add_add Rm1, Rn1, imm4, Rn2
+8.0xf7+8.0x10+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::add_add
+"add_add"
+*am33
+*am33_2
+{
+ int srcreg1, dstreg1, dstreg2;
+ int result1;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ result1 = State.regs[dstreg1] + State.regs[srcreg1];
+ State.regs[dstreg2] += EXTEND4 (IMM4);
+ State.regs[dstreg1] = result1;
+}
+
+// 1111 0111 0010 0000 Rm1 Rn1 Rm2 Rn2; add_sub Rm1, Rn1, Rm2, Rn2
+8.0xf7+8.0x20+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::add_sub
+"add_sub"
+*am33
+*am33_2
+{
+ int srcreg1, srcreg2, dstreg1, dstreg2;
+ int result1;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ srcreg2 = translate_rreg (SD_, RM2);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ result1 = State.regs[dstreg1] + State.regs[srcreg1];
+ State.regs[dstreg2] -= State.regs[srcreg2];
+ State.regs[dstreg1] = result1;