- {"add #<imm>,<REG_N>", "0111nnnni8*1....", "R[n] += SEXT(i);"},
- {"add <REG_M>,<REG_N>", "0011nnnnmmmm1100", "R[n] += R[m];"},
- {"addc <REG_M>,<REG_N>", "0011nnnnmmmm1110", "ult = R[n]; R[n] += (R[m]+T); T = ult>R[n];"},
- {"addv <REG_M>,<REG_N>", "0011nnnnmmmm1111",
- "long ans;",
- "ans = R[n] + R[m];",
- "T = ((~R[n] & R[m] & ans) | (R[n] & R[m] & ~ans)) >>31;",
- "R[n] = ans;"},
-
- {"and #<imm>,R0", "11001001i8*1....", "R0&=i;"},
- {"and <REG_M>,<REG_N>", "0010nnnnmmmm1001", "R[n]&=R[m];"},
- {"and.b #<imm>,@(R0,GBR)", "11001101i8*1....", "WBAT(GBR+R0, RBAT(GBR+R0) & i);"},
-
- {"bf <bdisp8>", "10001011i8p1....", "if(T==0) {PC+=(SEXT(i)<<1)+2;C+=2;}"},
- {"bra <bdisp12>", "1010i12.........", "ult = PC; PC=PC+(i<<1)+2;SL(ult+2);"},
- {"bsr <bdisp12>", "1011i12.........", "PR = PC; PC=PC+(i<<1)+2;SL(PR+2);"},
- {"bt <bdisp8>", "10001001i8p1....", "if(T==1) {PC+=(SEXT(i)<<1)+2;C+=2;}"},
- {"clrmac", "0000000000101000", "MACH = MACL = 0;"},
- {"clrt", "0000000000001000", "T= 0;"},
- {"cmp/eq #<imm>,R0", "10001000i8*1....", "T = R0 == SEXT(i);"},
- {"cmp/eq <REG_M>,<REG_N>", "0011nnnnmmmm0000", "T=R[n]==R[m];"},
- {"cmp/ge <REG_M>,<REG_N>", "0011nnnnmmmm0011", "T=R[n]>=R[m];"},
- {"cmp/gt <REG_M>,<REG_N>", "0011nnnnmmmm0111", "T=R[n]>R[m];"},
- {"cmp/hi <REG_M>,<REG_N>", "0011nnnnmmmm0110", "T=UR[n]>UR[m];"},
- {"cmp/hs <REG_M>,<REG_N>", "0011nnnnmmmm0010", "T=UR[n]>=UR[m];"},
- {"cmp/pl <REG_N>", "0100nnnn00010101", "T = R[n]>0;"},
- {"cmp/pz <REG_N>", "0100nnnn00010001", "T = R[n]>=0;"},
- {"cmp/str <REG_M>,<REG_N>", "0010nnnnmmmm1100", "ult = R[n] ^ R[m]; T=((ult&0xff000000)==0) |((ult&0xff0000)==0) |((ult&0xff00)==0) |((ult&0xff)==0); "},
- {"div0s <REG_M>,<REG_N>", "0010nnnnmmmm0111", "Q=R[n]<0; M=R[m]<0; T=M!=Q;;"},
- {"div0u", "0000000000011001", "M=Q=T=0;"},
- {"div1 <REG_M>,<REG_N>", "0011nnnnmmmm0100", "T=div1(R,n,m,T);"},
- {"exts.b <REG_M>,<REG_N>", "0110nnnnmmmm1110", "R[n] = SEXT(R[m]);"},
- {"exts.w <REG_M>,<REG_N>", "0110nnnnmmmm1111", "R[n] = SEXTW(R[m]);"},
- {"extu.b <REG_M>,<REG_N>", "0110nnnnmmmm1100", "R[n] = R[m] & 0xff;"},
- {"extu.w <REG_M>,<REG_N>", "0110nnnnmmmm1101", "R[n] = R[m] & 0xffff;"},
- {"jmp @<REG_N>", "0100nnnn00101011", "ult = PC; PC=R[n]-2; SL(ult+2);"},
- {"jsr @<REG_N>", "0100nnnn00001011", "PR = PC; PC=R[n]-2; SL(PR+2);"},
- {"ldc <REG_N>,GBR", "0100nnnn00011110", "GBR=R[n];"},
- {"ldc <REG_N>,SR", "0100nnnn00001110", "SET_SR(R[n]);"},
- {"ldc <REG_N>,VBR", "0100nnnn00101110", "VBR=R[n];"},
- {"ldc.l @<REG_N>+,GBR", "0100nnnn00010111", "GBR=RLAT(R[n]);R[n]+=4;;"},
- {"ldc.l @<REG_N>+,SR", "0100nnnn00000111", "SET_SR(RLAT(R[n]));R[n]+=4;;"},
- {"ldc.l @<REG_N>+,VBR", "0100nnnn00100111", "VBR=RLAT(R[n]);R[n]+=4;;"},
- {"lds <REG_N>,MACH", "0100nnnn00001010", "MACH = SEXT(R[n]);"},
- {"lds <REG_N>,MACL", "0100nnnn00011010", "MACL= R[n];"},
- {"lds <REG_N>,PR", "0100nnnn00101010", "PR = R[n];"},
- {"lds.l @<REG_N>+,MACH", "0100nnnn00000110", "MACH = SEXT(RLAT(R[n]));R[n]+=4;"},
- {"lds.l @<REG_N>+,MACL", "0100nnnn00010110", "MACL = RLAT(R[n]);R[n]+=4;"},
- {"lds.l @<REG_N>+,PR", "0100nnnn00100110", "PR = RLAT(R[n]);R[n]+=4;;"},
- {"mac.w @<REG_M>+,@<REG_N>+", "0100nnnnmmmm1111", "abort();"},
- {"mov #<imm>,<REG_N>", "1110nnnni8*1....", "R[n] = SEXT(i);"},
- {"mov <REG_M>,<REG_N>", "0110nnnnmmmm0011", "R[n] = R[m];"},
-{"mov.b <REG_M>,@(R0,<REG_N>)", "0000nnnnmmmm0100", "WBAT(R[n]+R0, R[m]);"},
-{"mov.b <REG_M>,@-<REG_N>", "0010nnnnmmmm0100", "R[n]--; WBAT(R[n], R[m]);"},
- {"mov.b <REG_M>,@<REG_N>", "0010nnnnmmmm0000", "WBAT(R[n], R[m]);"},
- {"mov.b @(<disp>,<REG_M>),R0", "10000100mmmmi4*1", "R0=RBAT(i+R[m]);"},
- {"mov.b @(<disp>,GBR),R0", "11000100i8*1....", "R0=RBAT(i+GBR);"},
- {"mov.b @(R0,<REG_M>),<REG_N>", "0000nnnnmmmm1100", "R[n]=RBAT(R0+R[m]);"},
-{"mov.b @<REG_M>+,<REG_N>", "0110nnnnmmmm0100", "R[n] = RBAT(R[m]);R[m]++;"},
- {"mov.b @<REG_M>,<REG_N>", "0110nnnnmmmm0000", "R[n]=RBAT(R[m]);"},
- {"mov.b R0,@(<disp>,<REG_M>)", "10000000mmmmi4*1", "R0=RBAT(i+R[m]);"},
- {"mov.b R0,@(<disp>,GBR)", "11000000i8*1....", "R0 = RBAT(i+GBR);"},
- {"mov.l <REG_M>,@(<disp>,<REG_N>)", "0001nnnnmmmmi4*4", "WLAT(i+R[n],R[m]);"},
- {"mov.l <REG_M>,@(R0,<REG_N>)", "0000nnnnmmmm0110", "WLAT(R0+R[n],R[m]);"},
-{"mov.l <REG_M>,@-<REG_N>", "0010nnnnmmmm0110", "R[n]-=4;WLAT(R[n],R[m]);"},
- {"mov.l <REG_M>,@<REG_N>", "0010nnnnmmmm0010", "WLAT(R[n], R[m]);"},
- {"mov.l @(<disp>,<REG_N>),<REG_M>", "0101nnnnmmmmi4*4", "R[m]=RLAT(i+R[n]);"},
- {"mov.l @(<disp>,GBR),R0", "11000110i4*4", "R0=RLAT(i+GBR);"},
- {"mov.l @(<disp>,PC),<REG_N>", "1101nnnni8p4....", "R[n]=RLAT(i+4+PC);"},
- {"mov.l @(R0,<REG_M>),<REG_N>", "0000nnnnmmmm1110", "R[n]=RLAT(R0+R[m]);"},
-{"mov.l @<REG_M>+,<REG_N>", "0110nnnnmmmm0110", "R[n]=RLAT(R[m]);R[m]+=4;"},
- {"mov.l @<REG_M>,<REG_N>", "0110nnnnmmmm0010", "R[n]=RLAT(R[m]);"},
- {"mov.l R0,@(<disp>,GBR)", "11000010i8*4....", "R0=RLAT(R0+GBR);"},
- {"mov.w <REG_M>,@(R0,<REG_N>)", "0000nnnnmmmm0101", "WWAT(R0+R[n],R[m]);"},
-{"mov.w <REG_M>,@-<REG_N>", "0010nnnnmmmm0101", "R[n]-=2;WWAT(R[n],R[m]);"},
- {"mov.w <REG_M>,@<REG_N>", "0010nnnnmmmm0001", "WWAT(R[n],R[m]);"},
- {"mov.w @(<disp>,<REG_M>),R0", "10000101mmmmi4*2", "R0=RSWAT(i+R[m]);"},
- {"mov.w @(<disp>,GBR),R0", "11000101i8*2....", "R0=RSWAT(i+GBR);"},
- {"mov.w @(<disp>,PC),<REG_N>", "1001nnnni8p2....", "R[n]=RSWAT(PC+i+4);"},
-{"mov.w @(R0,<REG_M>),<REG_N>", "0000nnnnmmmm1101", "R[n]=RSWAT(R0+R[m]);"},
-{"mov.w @<REG_M>+,<REG_N>", "0110nnnnmmmm0101", "R[n]=RSWAT(R[m]);R[m]+=2;"},
- {"mov.w @<REG_M>,<REG_N>", "0110nnnnmmmm0001", "R[n]=RSWAT(R[m]);"},
- {"mov.w R0,@(<disp>,<REG_M>)", "10000001mmmmi4*2", "R0=RSWAT(i+R[m]);"},
- {"mov.w R0,@(<disp>,GBR)", "11000001i8*2....", "R0=RSWAT(i+GBR);"},
- {"mova @(<disp>,PC),R0", "11000111i8p4....", "R0=i+4+PC;"},
- {"movt <REG_N>", "0000nnnn00101001", "R[n]=T;"},
- {"muls <REG_M>,<REG_N>", "0010nnnnmmmm1111",
- "MACL=((long)(short)R[n])*((long)(short)R[m]);"},
-{"mulu <REG_M>,<REG_N>","0010nnnnmmmm1110", "MACL=((unsigned long)(unsigned short)R[n])*((unsigned long)(unsigned short)R[m]);"},
- {"neg <REG_M>,<REG_N>", "0110nnnnmmmm1011", "R[n] = - R[m];"},
- {"negc <REG_M>,<REG_N>", "0110nnnnmmmm1010", "ult=0-R[m];R[n]=ult-T;T=SBIT(R[n])!=SBIT(ult);"},
- {"nop", "0000000000001001", ""},
- {"not <REG_M>,<REG_N>", "0110nnnnmmmm0111", "R[n]=~R[m];"},
- {"or #<imm>,R0", "11001011i8*1....", "R0|=i;"},
- {"or <REG_M>,<REG_N>", "0010nnnnmmmm1011", "R[n]|=R[m];"},
- {"or.b #<imm>,@(R0,GBR)", "11001111i8*1....", "WBAT(R0+GBR,RBAT(R0+GBR)|i);"},
- {"rotcl <REG_N>", "0100nnnn00100100", "ult = R[n] <0;R[n] = (R[n]<<1)|T;T=ult;"},
- {"rotcr <REG_N>", "0100nnnn00100101", "ult = R[n]&1;R[n]=(UR[n]>>1)|(T<<31);T=ult;"},
- {"rotl <REG_N>", "0100nnnn00000100", "T=R[n]<0;R[n]<<=1;R[n]|=T;"},
- {"rotr <REG_N>", "0100nnnn00000101", "T=R[n]&1;UR[n]>>=1;R[n]|=(T<<31);"},
- {"rte", "0000000000101011", "abort();"},
- {"rts", "0000000000001011", "ult=PC;PC=PR+2;SL(ult+2);"},
- {"sett", "0000000000011000", "T=1;"},
- {"shal <REG_N>", "0100nnnn00100000", "T=R[n]<0; R[n]<<=1;"},
- {"shar <REG_N>", "0100nnnn00100001", "T=R[n]&1; R[n]>>=1;"},
- {"shll <REG_N>", "0100nnnn00000000", "T=R[n]<0; R[n]<<=1;"},
- {"shll16 <REG_N>", "0100nnnn00101000", "R[n]<<=16;"},
- {"shll2 <REG_N>", "0100nnnn00001000", "R[n]<<=2;"},
- {"shll8 <REG_N>", "0100nnnn00011000", "R[n]<<=8;"},
- {"shlr <REG_N>", "0100nnnn00000001", "T=R[n]&1;R[n]=UR[n]>>1;"},
- {"shlr16 <REG_N>", "0100nnnn00101001", "R[n]=UR[n]>>16;"},
- {"shlr2 <REG_N>", "0100nnnn00001001", "R[n]=UR[n]>>2;"},
- {"shlr8 <REG_N>", "0100nnnn00011001", "R[n]=UR[n]>>8;"},
- {"sleep", "0000000000011011", "abort();"},
- {"stc GBR,<REG_N>", "0000nnnn00010010", "R[n]=GBR;"},
- {"stc SR,<REG_N>", "0000nnnn00000010", "R[n]=GET_SR();"},
- {"stc VBR,<REG_N>", "0000nnnn00100010", "R[n]=VBR;"},
- {"stc.l GBR,@-<REG_N>", "0100nnnn00010011", "R[n]-=4;WLAT(R[n],GBR);;"},
- {"stc.l SR,@-<REG_N>", "0100nnnn00000011", "R[n]-=4;WLAT(R[n],GET_SR());"},
- {"stc.l VBR,@-<REG_N>", "0100nnnn00100011", "R[n]-=4;WLAT(R[n],VBR);"},
- {"sts MACH,<REG_N>", "0000nnnn00001010", "R[n]=MACH;"},
- {"sts MACL,<REG_N>", "0000nnnn00011010", "R[n]=MACL;"},
- {"sts PR,<REG_N>", "0000nnnn00101010", "R[n]=PR;"},
- {"sts.l MACH,@-<REG_N>", "0100nnnn00000010", "R[n]-=4;WLAT(R[n],MACH);"},
- {"sts.l MACL,@-<REG_N>", "0100nnnn00010010", "R[n]-=4;WLAT(R[n],MACL);"},
- {"sts.l PR,@-<REG_N>", "0100nnnn00100010", "R[n]-=4;WLAT(R[n],PR);"},
- {"sub <REG_M>,<REG_N>", "0011nnnnmmmm1000", "R[n]-=R[m];"},
- {"subc <REG_M>,<REG_N>", "0011nnnnmmmm1010", "ult = R[n];R[n]-=R[m]+T;T=ult<UR[n];"},
- {"subv <REG_M>,<REG_N>", "0011nnnnmmmm1011", "abort();"},
- {"swap.b <REG_M>,<REG_N>", "0110nnnnmmmm1000", "R[n]=((R[m]<<8)&0xff00)|((R[m]>>8)&0x00ff);"},
- {"swap.w <REG_M>,<REG_N>", "0110nnnnmmmm1001", "R[n]=((R[m]<<16)&0xffff0000)|((R[m]>>16)&0x00ffff);"},
- {"tas.b @<REG_N>", "0100nnnn00011011", "ult=RBAT(R[n]);T=ult==0;WBAT(R[n],ult|0x80);"},
- {"trapa #<imm>", "11000011i8*1....", "trap(i,R);"},
- {"tst #<imm>,R0", "11001000i8*1....", "T=(R0&i)==0;"},
- {"tst <REG_M>,<REG_N>", "0010nnnnmmmm1000", "T=(R[n]&R[m])==0;"},
- {"tst.b #<imm>,@(R0,GBR)", "11001100i8*1....", "T=(RBAT(GBR+R0)&i)==0;"},
- {"xor #<imm>,R0", "11001010i8*1....", "R0^=i;"},
- {"xor <REG_M>,<REG_N>", "0010nnnnmmmm1010", "R[n]^=R[m];"},
- {"xor.b #<imm>,@(R0,GBR)", "11001110i8*1....", "ult=RBAT(GBR+R0);ult^=i;WBAT(GBR+R0,ult);"},
- {"xtrct <REG_M>,<REG_N>", "0010nnnnmmmm1101", "R[n]=((R[n]>>16)&0xffff)|((R[m]<<16)&0xffff0000);"},
+ { "n", "", "add #<imm>,<REG_N>", "0111nnnni8*1....",
+ "R[n] += SEXT (i);",
+ "if (i == 0) {",
+ " UNDEF(n); /* see #ifdef PARANOID */",
+ " break;",
+ "}",
+ },
+ { "n", "mn", "add <REG_M>,<REG_N>", "0011nnnnmmmm1100",
+ "R[n] += R[m];",
+ },
+
+ { "n", "mn", "addc <REG_M>,<REG_N>", "0011nnnnmmmm1110",
+ "ult = R[n] + T;",
+ "SET_SR_T (ult < R[n]);",
+ "R[n] = ult + R[m];",
+ "SET_SR_T (T || (R[n] < ult));",
+ },
+
+ { "n", "mn", "addv <REG_M>,<REG_N>", "0011nnnnmmmm1111",
+ "ult = R[n] + R[m];",
+ "SET_SR_T ((~(R[n] ^ R[m]) & (ult ^ R[n])) >> 31);",
+ "R[n] = ult;",
+ },
+
+ { "0", "0", "and #<imm>,R0", "11001001i8*1....",
+ "R0 &= i;",
+ },
+ { "n", "nm", "and <REG_M>,<REG_N>", "0010nnnnmmmm1001",
+ "R[n] &= R[m];",
+ },
+ { "", "0", "and.b #<imm>,@(R0,GBR)", "11001101i8*1....",
+ "MA (1);",
+ "WBAT (GBR + R0, RBAT (GBR + R0) & i);",
+ },
+
+ { "", "", "bf <bdisp8>", "10001011i8p1....",
+ "RAISE_EXCEPTION_IF_IN_DELAY_SLOT ();",
+ "if (!T) {",
+ " SET_NIP (PC + 4 + (SEXT (i) * 2));",
+ " cycles += 2;",
+ "}",
+ },
+
+ { "", "", "bf.s <bdisp8>", "10001111i8p1....",
+ "RAISE_EXCEPTION_IF_IN_DELAY_SLOT ();",
+ "if (!T) {",
+ " SET_NIP (PC + 4 + (SEXT (i) * 2));",
+ " cycles += 2;",
+ " Delay_Slot (PC + 2);",
+ "}",
+ },
+
+ { "", "n", "bit32 #imm3,@(disp12,<REG_N>)", "0011nnnni8*11001",
+ "/* 32-bit logical bit-manipulation instructions. */",
+ "int word2 = RIAT (nip);",
+ "RAISE_EXCEPTION_IF_IN_DELAY_SLOT ();",
+ "i >>= 4; /* BOGUS: Using only three bits of 'i'. */",
+ "/* MSB of 'i' must be zero. */",
+ "if (i > 7)",
+ " RAISE_EXCEPTION (SIGILL);",
+ "MA (1);",
+ "do_blog_insn (1 << i, (word2 & 0xfff) + R[n], ",
+ " (word2 >> 12) & 0xf, memory, maskb);",
+ "SET_NIP (nip + 2); /* Consume 2 more bytes. */",
+ },
+ { "", "", "bra <bdisp12>", "1010i12.........",
+ "RAISE_EXCEPTION_IF_IN_DELAY_SLOT ();",
+ "SET_NIP (PC + 4 + (SEXT12 (i) * 2));",
+ "cycles += 2;",
+ "Delay_Slot (PC + 2);",
+ },
+
+ { "", "n", "braf <REG_N>", "0000nnnn00100011",
+ "RAISE_EXCEPTION_IF_IN_DELAY_SLOT ();",
+ "SET_NIP (PC + 4 + R[n]);",
+ "cycles += 2;",
+ "Delay_Slot (PC + 2);",
+ },
+
+ { "", "", "bsr <bdisp12>", "1011i12.........",
+ "RAISE_EXCEPTION_IF_IN_DELAY_SLOT ();",
+ "PR = PH2T (PC + 4);",
+ "SET_NIP (PC + 4 + (SEXT12 (i) * 2));",
+ "cycles += 2;",
+ "Delay_Slot (PC + 2);",
+ },
+
+ { "", "n", "bsrf <REG_N>", "0000nnnn00000011",
+ "RAISE_EXCEPTION_IF_IN_DELAY_SLOT ();",
+ "PR = PH2T (PC) + 4;",
+ "SET_NIP (PC + 4 + R[n]);",
+ "cycles += 2;",
+ "Delay_Slot (PC + 2);",
+ },
+
+ { "", "", "bt <bdisp8>", "10001001i8p1....",
+ "RAISE_EXCEPTION_IF_IN_DELAY_SLOT ();",
+ "if (T) {",
+ " SET_NIP (PC + 4 + (SEXT (i) * 2));",
+ " cycles += 2;",
+ "}",
+ },
+
+ { "", "m", "bld/st #<imm>, <REG_M>", "10000111mmmmi4*1",
+ "/* MSB of 'i' is true for load, false for store. */",
+ "if (i <= 7)",
+ " if (T)",
+ " R[m] |= (1 << i);",
+ " else",
+ " R[m] &= ~(1 << i);",
+ "else",
+ " SET_SR_T ((R[m] & (1 << (i - 8))) != 0);",
+ },
+ { "m", "m", "bset/clr #<imm>, <REG_M>", "10000110mmmmi4*1",
+ "/* MSB of 'i' is true for set, false for clear. */",
+ "if (i <= 7)",
+ " R[m] &= ~(1 << i);",
+ "else",
+ " R[m] |= (1 << (i - 8));",
+ },
+ { "n", "n", "clips.b <REG_N>", "0100nnnn10010001",
+ "if (R[n] < -128 || R[n] > 127) {",
+ " L (n);",
+ " SET_SR_CS (1);",
+ " if (R[n] > 127)",
+ " R[n] = 127;",
+ " else if (R[n] < -128)",
+ " R[n] = -128;",
+ "}",
+ },
+ { "n", "n", "clips.w <REG_N>", "0100nnnn10010101",
+ "if (R[n] < -32768 || R[n] > 32767) {",
+ " L (n);",
+ " SET_SR_CS (1);",
+ " if (R[n] > 32767)",
+ " R[n] = 32767;",
+ " else if (R[n] < -32768)",
+ " R[n] = -32768;",
+ "}",
+ },
+ { "n", "n", "clipu.b <REG_N>", "0100nnnn10000001",
+ "if (R[n] < -256 || R[n] > 255) {",
+ " L (n);",
+ " SET_SR_CS (1);",
+ " R[n] = 255;",
+ "}",
+ },
+ { "n", "n", "clipu.w <REG_N>", "0100nnnn10000101",
+ "if (R[n] < -65536 || R[n] > 65535) {",
+ " L (n);",
+ " SET_SR_CS (1);",
+ " R[n] = 65535;",
+ "}",
+ },
+ { "n", "0n", "divs R0,<REG_N>", "0100nnnn10010100",
+ "RAISE_EXCEPTION_IF_IN_DELAY_SLOT ();",
+ "if (R0 == 0)",
+ " R[n] = 0x7fffffff;",
+ "else if (R0 == -1 && R[n] == 0x80000000)",
+ " R[n] = 0x7fffffff;",
+ "else R[n] /= R0;",
+ "L (n);",
+ },
+ { "n", "0n", "divu R0,<REG_N>", "0100nnnn10000100",
+ "RAISE_EXCEPTION_IF_IN_DELAY_SLOT ();",
+ "if (R0 == 0)",
+ " R[n] = 0xffffffff;",
+ "/* FIXME: The result may be implementation-defined if it is outside */",
+ "/* the range of signed int (i.e. if R[n] was negative and R0 == 1). */",
+ "else R[n] = R[n] / (unsigned int) R0;",
+ "L (n);",
+ },
+ { "n", "0n", "mulr R0,<REG_N>", "0100nnnn10000000",
+ "R[n] = (R[n] * R0) & 0xffffffff;",
+ "L (n);",
+ },
+ { "0", "n", "ldbank @<REG_N>,R0", "0100nnnn11100101",
+ "int regn = (R[n] >> 2) & 0x1f;",
+ "int bankn = (R[n] >> 7) & 0x1ff;",
+ "if (regn > 19)",
+ " regn = 19; /* FIXME what should happen? */",
+ "R0 = saved_state.asregs.regstack[bankn].regs[regn];",
+ "L (0);",
+ },
+ { "", "0n", "stbank R0,@<REG_N>", "0100nnnn11100001",
+ "int regn = (R[n] >> 2) & 0x1f;",
+ "int bankn = (R[n] >> 7) & 0x1ff;",
+ "if (regn > 19)",
+ " regn = 19; /* FIXME what should happen? */",
+ "saved_state.asregs.regstack[bankn].regs[regn] = R0;",
+ },
+ { "", "", "resbank", "0000000001011011",
+ "int i;",
+ "RAISE_EXCEPTION_IF_IN_DELAY_SLOT ();",
+ /* FIXME: cdef all */
+ "if (BO) { /* Bank Overflow */",
+ /* FIXME: how do we know when to reset BO? */
+ " for (i = 0; i <= 14; i++) {",
+ " R[i] = RLAT (R[15]);",
+ " MA (1);",
+ " R[15] += 4;",
+ " }",
+ " PR = RLAT (R[15]);",
+ " R[15] += 4;",
+ " MA (1);",
+ " GBR = RLAT (R[15]);",
+ " R[15] += 4;",
+ " MA (1);",
+ " MACH = RLAT (R[15]);",
+ " R[15] += 4;",
+ " MA (1);",
+ " MACL = RLAT (R[15]);",
+ " R[15] += 4;",
+ " MA (1);",
+ "}",
+ "else if (BANKN == 0) /* Bank Underflow */",
+ " RAISE_EXCEPTION (SIGILL);", /* FIXME: what exception? */
+ "else {",
+ " SET_BANKN (BANKN - 1);",
+ " for (i = 0; i <= 14; i++)",
+ " R[i] = saved_state.asregs.regstack[BANKN].regs[i];",
+ " MACH = saved_state.asregs.regstack[BANKN].regs[15];",
+ " PR = saved_state.asregs.regstack[BANKN].regs[17];",
+ " GBR = saved_state.asregs.regstack[BANKN].regs[18];",
+ " MACL = saved_state.asregs.regstack[BANKN].regs[19];",
+ "}",
+ },
+ { "f", "f-", "movml.l <REG_N>,@-R15", "0100nnnn11110001",
+ "/* Push Rn...R0 (if n==15, push pr and R14...R0). */",
+ "do {",
+ " MA (1);",
+ " R[15] -= 4;",
+ " if (n == 15)",
+ " WLAT (R[15], PR);",
+ " else",
+ " WLAT (R[15], R[n]);",
+ "} while (n-- > 0);",
+ },
+ { "f", "f+", "movml.l @R15+,<REG_N>", "0100nnnn11110101",
+ "/* Pop R0...Rn (if n==15, pop R0...R14 and pr). */",
+ "int i = 0;\n",
+ "do {",
+ " MA (1);",
+ " if (i == 15)",
+ " PR = RLAT (R[15]);",
+ " else",
+ " R[i] = RLAT (R[15]);",
+ " R[15] += 4;",
+ "} while (i++ < n);",
+ },
+ { "f", "f-", "movmu.l <REG_N>,@-R15", "0100nnnn11110000",
+ "/* Push pr, R14...Rn (if n==15, push pr). */", /* FIXME */
+ "int i = 15;\n",
+ "do {",
+ " MA (1);",
+ " R[15] -= 4;",
+ " if (i == 15)",
+ " WLAT (R[15], PR);",
+ " else",
+ " WLAT (R[15], R[i]);",
+ "} while (i-- > n);",
+ },
+ { "f", "f+", "movmu.l @R15+,<REG_N>", "0100nnnn11110100",
+ "/* Pop Rn...R14, pr (if n==15, pop pr). */", /* FIXME */
+ "do {",
+ " MA (1);",
+ " if (n == 15)",
+ " PR = RLAT (R[15]);",
+ " else",
+ " R[n] = RLAT (R[15]);",
+ " R[15] += 4;",
+ "} while (n++ < 15);",
+ },
+ { "", "", "nott", "0000000001101000",
+ "SET_SR_T (T == 0);",
+ },
+
+ { "", "", "bt.s <bdisp8>", "10001101i8p1....",
+ "RAISE_EXCEPTION_IF_IN_DELAY_SLOT ();",
+ "if (T) {",
+ " SET_NIP (PC + 4 + (SEXT (i) * 2));",
+ " cycles += 2;",
+ " Delay_Slot (PC + 2);",
+ "}",
+ },
+
+ { "", "", "clrmac", "0000000000101000",
+ "MACH = 0;",
+ "MACL = 0;",
+ },
+
+ { "", "", "clrs", "0000000001001000",
+ "SET_SR_S (0);",
+ },
+
+ { "", "", "clrt", "0000000000001000",
+ "SET_SR_T (0);",
+ },
+
+ /* sh4a */
+ { "", "", "clrdmxy", "0000000010001000",
+ "saved_state.asregs.cregs.named.sr &= ~(SR_MASK_DMX | SR_MASK_DMY);"
+ },
+
+ { "", "0", "cmp/eq #<imm>,R0", "10001000i8*1....",
+ "SET_SR_T (R0 == SEXT (i));",
+ },
+ { "", "mn", "cmp/eq <REG_M>,<REG_N>", "0011nnnnmmmm0000",
+ "SET_SR_T (R[n] == R[m]);",
+ },
+ { "", "mn", "cmp/ge <REG_M>,<REG_N>", "0011nnnnmmmm0011",
+ "SET_SR_T (R[n] >= R[m]);",
+ },
+ { "", "mn", "cmp/gt <REG_M>,<REG_N>", "0011nnnnmmmm0111",
+ "SET_SR_T (R[n] > R[m]);",
+ },
+ { "", "mn", "cmp/hi <REG_M>,<REG_N>", "0011nnnnmmmm0110",
+ "SET_SR_T (UR[n] > UR[m]);",
+ },
+ { "", "mn", "cmp/hs <REG_M>,<REG_N>", "0011nnnnmmmm0010",
+ "SET_SR_T (UR[n] >= UR[m]);",
+ },
+ { "", "n", "cmp/pl <REG_N>", "0100nnnn00010101",
+ "SET_SR_T (R[n] > 0);",
+ },
+ { "", "n", "cmp/pz <REG_N>", "0100nnnn00010001",
+ "SET_SR_T (R[n] >= 0);",
+ },
+ { "", "mn", "cmp/str <REG_M>,<REG_N>", "0010nnnnmmmm1100",
+ "ult = R[n] ^ R[m];",
+ "SET_SR_T (((ult & 0xff000000) == 0)",
+ " | ((ult & 0xff0000) == 0)",
+ " | ((ult & 0xff00) == 0)",
+ " | ((ult & 0xff) == 0));",
+ },
+
+ { "", "mn", "div0s <REG_M>,<REG_N>", "0010nnnnmmmm0111",
+ "SET_SR_Q ((R[n] & sbit) != 0);",
+ "SET_SR_M ((R[m] & sbit) != 0);",
+ "SET_SR_T (M != Q);",
+ },
+
+ { "", "", "div0u", "0000000000011001",
+ "SET_SR_M (0);",
+ "SET_SR_Q (0);",
+ "SET_SR_T (0);",
+ },
+
+ { "n", "nm", "div1 <REG_M>,<REG_N>", "0011nnnnmmmm0100",
+ "div1 (&R0, m, n/*, T*/);",
+ },
+
+ { "", "nm", "dmuls.l <REG_M>,<REG_N>", "0011nnnnmmmm1101",
+ "dmul_s (R[n], R[m]);",
+ },
+
+ { "", "nm", "dmulu.l <REG_M>,<REG_N>", "0011nnnnmmmm0101",
+ "dmul_u (R[n], R[m]);",
+ },
+
+ { "n", "n", "dt <REG_N>", "0100nnnn00010000",
+ "R[n]--;",
+ "SET_SR_T (R[n] == 0);",
+ },
+
+ { "n", "m", "exts.b <REG_M>,<REG_N>", "0110nnnnmmmm1110",
+ "R[n] = SEXT (R[m]);",
+ },
+ { "n", "m", "exts.w <REG_M>,<REG_N>", "0110nnnnmmmm1111",
+ "R[n] = SEXTW (R[m]);",
+ },
+
+ { "n", "m", "extu.b <REG_M>,<REG_N>", "0110nnnnmmmm1100",
+ "R[n] = (R[m] & 0xff);",
+ },
+ { "n", "m", "extu.w <REG_M>,<REG_N>", "0110nnnnmmmm1101",
+ "R[n] = (R[m] & 0xffff);",
+ },
+
+ /* sh2e */
+ { "", "", "fabs <FREG_N>", "1111nnnn01011101",
+ " union",
+ " {",
+ " unsigned int i;",
+ " float f;",
+ " } u;",
+ " u.f = FR (n);",
+ " u.i &= 0x7fffffff;",
+ " SET_FR (n, u.f);",
+ },
+
+ /* sh2e */
+ { "", "", "fadd <FREG_M>,<FREG_N>", "1111nnnnmmmm0000",
+ "FP_OP (n, +, m);",
+ },
+
+ /* sh2e */
+ { "", "", "fcmp/eq <FREG_M>,<FREG_N>", "1111nnnnmmmm0100",
+ "FP_CMP (n, ==, m);",
+ },
+ /* sh2e */
+ { "", "", "fcmp/gt <FREG_M>,<FREG_N>", "1111nnnnmmmm0101",
+ "FP_CMP (n, >, m);",
+ },
+
+ /* sh4 */
+ { "", "", "fcnvds <DR_N>,FPUL", "1111nnnn10111101",
+ "if (! FPSCR_PR || n & 1)",
+ " RAISE_EXCEPTION (SIGILL);",
+ "else",
+ "{",
+ " union",
+ " {",
+ " int i;",
+ " float f;",
+ " } u;",
+ " u.f = DR (n);",
+ " FPUL = u.i;",
+ "}",
+ },
+
+ /* sh4 */
+ { "", "", "fcnvsd FPUL,<DR_N>", "1111nnnn10101101",
+ "if (! FPSCR_PR || n & 1)",
+ " RAISE_EXCEPTION (SIGILL);",
+ "else",
+ "{",
+ " union",
+ " {",
+ " int i;",
+ " float f;",
+ " } u;",
+ " u.i = FPUL;",
+ " SET_DR (n, u.f);",
+ "}",
+ },
+
+ /* sh2e */
+ { "", "", "fdiv <FREG_M>,<FREG_N>", "1111nnnnmmmm0011",
+ "FP_OP (n, /, m);",
+ "/* FIXME: check for DP and (n & 1) == 0? */",
+ },
+
+ /* sh4 */
+ { "", "", "fipr <FV_M>,<FV_N>", "1111vvVV11101101",
+ "if (FPSCR_PR)",
+ " RAISE_EXCEPTION (SIGILL);",
+ "else",
+ "{",
+ " double fsum = 0;",
+ " if (saved_state.asregs.bfd_mach == bfd_mach_sh2a)",
+ " RAISE_EXCEPTION (SIGILL);",
+ " /* FIXME: check for nans and infinities. */",
+ " fsum += FR (v1+0) * FR (v2+0);",
+ " fsum += FR (v1+1) * FR (v2+1);",
+ " fsum += FR (v1+2) * FR (v2+2);",
+ " fsum += FR (v1+3) * FR (v2+3);",
+ " SET_FR (v1+3, fsum);",
+ "}",
+ },
+
+ /* sh2e */
+ { "", "", "fldi0 <FREG_N>", "1111nnnn10001101",
+ "SET_FR (n, (float) 0.0);",
+ "/* FIXME: check for DP and (n & 1) == 0? */",
+ },
+
+ /* sh2e */
+ { "", "", "fldi1 <FREG_N>", "1111nnnn10011101",
+ "SET_FR (n, (float) 1.0);",
+ "/* FIXME: check for DP and (n & 1) == 0? */",
+ },
+
+ /* sh2e */
+ { "", "", "flds <FREG_N>,FPUL", "1111nnnn00011101",
+ " union",
+ " {",
+ " int i;",
+ " float f;",
+ " } u;",
+ " u.f = FR (n);",
+ " FPUL = u.i;",
+ },
+
+ /* sh2e */
+ { "", "", "float FPUL,<FREG_N>", "1111nnnn00101101",
+ /* sh4 */
+ "if (FPSCR_PR)",
+ " SET_DR (n, (double) FPUL);",
+ "else",
+ "{",
+ " SET_FR (n, (float) FPUL);",
+ "}",
+ },
+
+ /* sh2e */
+ { "", "", "fmac <FREG_0>,<FREG_M>,<FREG_N>", "1111nnnnmmmm1110",
+ "SET_FR (n, FR (m) * FR (0) + FR (n));",
+ "/* FIXME: check for DP and (n & 1) == 0? */",
+ },
+
+ /* sh2e */
+ { "", "", "fmov <FREG_M>,<FREG_N>", "1111nnnnmmmm1100",
+ /* sh4 */
+ "if (FPSCR_SZ) {",
+ " int ni = XD_TO_XF (n);",
+ " int mi = XD_TO_XF (m);",
+ " SET_XF (ni + 0, XF (mi + 0));",
+ " SET_XF (ni + 1, XF (mi + 1));",
+ "}",
+ "else",
+ "{",
+ " SET_FR (n, FR (m));",
+ "}",
+ },
+ /* sh2e */
+ { "", "n", "fmov.s <FREG_M>,@<REG_N>", "1111nnnnmmmm1010",
+ /* sh4 */
+ "if (FPSCR_SZ) {",
+ " MA (2);",
+ " WDAT (R[n], m);",
+ "}",
+ "else",
+ "{",
+ " MA (1);",
+ " WLAT (R[n], FI (m));",
+ "}",
+ },
+ /* sh2e */
+ { "", "m", "fmov.s @<REG_M>,<FREG_N>", "1111nnnnmmmm1000",
+ /* sh4 */
+ "if (FPSCR_SZ) {",
+ " MA (2);",
+ " RDAT (R[m], n);",
+ "}",
+ "else",
+ "{",
+ " MA (1);",
+ " SET_FI (n, RLAT (R[m]));",
+ "}",
+ },
+ /* sh2a */
+ { "", "n", "fmov.s @(disp12,<REG_N>), <FREG_M>", "0011nnnnmmmm0001",
+ "/* and fmov.s <FREG_N>, @(disp12,<FREG_M>)",
+ " and mov.bwl <REG_N>, @(disp12,<REG_M>)",
+ " and mov.bwl @(disp12,<REG_N>),<REG_M>",
+ " and movu.bw @(disp12,<REG_N>),<REG_M>. */",
+ "int word2 = RIAT (nip);",
+ "RAISE_EXCEPTION_IF_IN_DELAY_SLOT ();",
+ "SET_NIP (nip + 2); /* Consume 2 more bytes. */",
+ "MA (1);",
+ "do_long_move_insn (word2 & 0xf000, word2 & 0x0fff, m, n, &thislock);",
+ },
+ /* sh2e */
+ { "m", "m", "fmov.s @<REG_M>+,<FREG_N>", "1111nnnnmmmm1001",
+ /* sh4 */
+ "if (FPSCR_SZ) {",
+ " MA (2);",
+ " RDAT (R[m], n);",
+ " R[m] += 8;",
+ "}",
+ "else",
+ "{",
+ " MA (1);",
+ " SET_FI (n, RLAT (R[m]));",
+ " R[m] += 4;",
+ "}",
+ },
+ /* sh2e */
+ { "n", "n", "fmov.s <FREG_M>,@-<REG_N>", "1111nnnnmmmm1011",
+ /* sh4 */
+ "if (FPSCR_SZ) {",
+ " MA (2);",
+ " R[n] -= 8;",
+ " WDAT (R[n], m);",
+ "}",
+ "else",
+ "{",
+ " MA (1);",
+ " R[n] -= 4;",
+ " WLAT (R[n], FI (m));",
+ "}",
+ },
+ /* sh2e */
+ { "", "0m", "fmov.s @(R0,<REG_M>),<FREG_N>", "1111nnnnmmmm0110",
+ /* sh4 */
+ "if (FPSCR_SZ) {",
+ " MA (2);",
+ " RDAT (R[0]+R[m], n);",
+ "}",
+ "else",
+ "{",
+ " MA (1);",
+ " SET_FI (n, RLAT (R[0] + R[m]));",
+ "}",
+ },
+ /* sh2e */
+ { "", "0n", "fmov.s <FREG_M>,@(R0,<REG_N>)", "1111nnnnmmmm0111",
+ /* sh4 */
+ "if (FPSCR_SZ) {",
+ " MA (2);",
+ " WDAT (R[0]+R[n], m);",
+ "}",
+ "else",
+ "{",
+ " MA (1);",
+ " WLAT ((R[0]+R[n]), FI (m));",
+ "}",
+ },
+
+ /* sh4:
+ See fmov instructions above for move to/from extended fp registers. */
+
+ /* sh2e */
+ { "", "", "fmul <FREG_M>,<FREG_N>", "1111nnnnmmmm0010",
+ "FP_OP (n, *, m);",
+ },
+
+ /* sh2e */
+ { "", "", "fneg <FREG_N>", "1111nnnn01001101",
+ " union",
+ " {",
+ " unsigned int i;",
+ " float f;",
+ " } u;",
+ " u.f = FR (n);",
+ " u.i ^= 0x80000000;",
+ " SET_FR (n, u.f);",
+ },
+
+ /* sh4a */
+ { "", "", "fpchg", "1111011111111101",
+ "SET_FPSCR (GET_FPSCR () ^ FPSCR_MASK_PR);",
+ },
+
+ /* sh4 */
+ { "", "", "frchg", "1111101111111101",
+ "if (FPSCR_PR)",
+ " RAISE_EXCEPTION (SIGILL);",
+ "else if (saved_state.asregs.bfd_mach == bfd_mach_sh2a)",
+ " RAISE_EXCEPTION (SIGILL);",
+ "else",
+ " SET_FPSCR (GET_FPSCR () ^ FPSCR_MASK_FR);",
+ },
+
+ /* sh4 */
+ { "", "", "fsca", "1111eeee11111101",
+ "if (FPSCR_PR)",
+ " RAISE_EXCEPTION (SIGILL);",
+ "else if (saved_state.asregs.bfd_mach == bfd_mach_sh2a)",
+ " RAISE_EXCEPTION (SIGILL);",
+ "else",
+ " {",
+ " SET_FR (n, fsca_s (FPUL, &sin));",
+ " SET_FR (n+1, fsca_s (FPUL, &cos));",
+ " }",
+ },
+
+ /* sh4 */
+ { "", "", "fschg", "1111001111111101",
+ "SET_FPSCR (GET_FPSCR () ^ FPSCR_MASK_SZ);",
+ },
+
+ /* sh3e */
+ { "", "", "fsqrt <FREG_N>", "1111nnnn01101101",
+ "FP_UNARY (n, sqrt);",
+ },
+
+ /* sh4 */
+ { "", "", "fsrra <FREG_N>", "1111nnnn01111101",
+ "if (FPSCR_PR)",
+ " RAISE_EXCEPTION (SIGILL);",
+ "else if (saved_state.asregs.bfd_mach == bfd_mach_sh2a)",
+ " RAISE_EXCEPTION (SIGILL);",
+ "else",
+ " SET_FR (n, fsrra_s (FR (n)));",
+ },
+
+ /* sh2e */
+ { "", "", "fsub <FREG_M>,<FREG_N>", "1111nnnnmmmm0001",
+ "FP_OP (n, -, m);",
+ },
+
+ /* sh2e */
+ { "", "", "ftrc <FREG_N>, FPUL", "1111nnnn00111101",
+ /* sh4 */
+ "if (FPSCR_PR) {",
+ " if (DR (n) != DR (n)) /* NaN */",
+ " FPUL = 0x80000000;",
+ " else",
+ " FPUL = (int) DR (n);",
+ "}",
+ "else",
+ "if (FR (n) != FR (n)) /* NaN */",
+ " FPUL = 0x80000000;",
+ "else",
+ " FPUL = (int) FR (n);",
+ },
+
+ /* sh4 */
+ { "", "", "ftrv <FV_N>", "1111vv0111111101",
+ "if (FPSCR_PR)",
+ " RAISE_EXCEPTION (SIGILL);",
+ "else",
+ "{",
+ " if (saved_state.asregs.bfd_mach == bfd_mach_sh2a)",
+ " RAISE_EXCEPTION (SIGILL);",
+ " /* FIXME not implemented. */",
+ " printf (\"ftrv xmtrx, FV%d\\n\", v1);",
+ "}",
+ },
+
+ /* sh2e */
+ { "", "", "fsts FPUL,<FREG_N>", "1111nnnn00001101",
+ " union",
+ " {",
+ " int i;",
+ " float f;",
+ " } u;",
+ " u.i = FPUL;",
+ " SET_FR (n, u.f);",
+ },
+
+ { "", "n", "jmp @<REG_N>", "0100nnnn00101011",
+ "RAISE_EXCEPTION_IF_IN_DELAY_SLOT ();",
+ "SET_NIP (PT2H (R[n]));",
+ "cycles += 2;",
+ "Delay_Slot (PC + 2);",
+ },
+
+ { "", "n", "jsr @<REG_N>", "0100nnnn00001011",
+ "RAISE_EXCEPTION_IF_IN_DELAY_SLOT ();",
+ "PR = PH2T (PC + 4);",
+ "if (~doprofile)",
+ " gotcall (PR, R[n]);",
+ "SET_NIP (PT2H (R[n]));",
+ "cycles += 2;",
+ "Delay_Slot (PC + 2);",
+ },
+ { "", "n", "jsr/n @<REG_N>", "0100nnnn01001011",
+ "RAISE_EXCEPTION_IF_IN_DELAY_SLOT ();",
+ "PR = PH2T (PC + 2);",
+ "if (~doprofile)",
+ " gotcall (PR, R[n]);",
+ "SET_NIP (PT2H (R[n]));",
+ },
+ { "", "", "jsr/n @@(<disp>,TBR)", "10000011i8p4....",
+ "RAISE_EXCEPTION_IF_IN_DELAY_SLOT ();",
+ "PR = PH2T (PC + 2);",
+ "if (~doprofile)",
+ " gotcall (PR, i + TBR);",
+ "SET_NIP (PT2H (i + TBR));",
+ },
+
+ { "", "n", "ldc <REG_N>,<CREG_M>", "0100nnnnmmmm1110",
+ "CREG (m) = R[n];",
+ "/* FIXME: user mode */",
+ },
+ { "", "n", "ldc <REG_N>,SR", "0100nnnn00001110",
+ "SET_SR (R[n]);",
+ "/* FIXME: user mode */",
+ },
+ { "", "n", "ldc <REG_N>,MOD", "0100nnnn01011110",
+ "SET_MOD (R[n]);",
+ },
+ { "", "n", "ldc <REG_N>,DBR", "0100nnnn11111010",
+ "if (SR_MD)",
+ " DBR = R[n]; /* priv mode */",
+ "else",
+ " RAISE_EXCEPTION (SIGILL); /* user mode */",
+ },
+ { "", "n", "ldc <REG_N>,SGR", "0100nnnn00111010",
+ "if (SR_MD)",
+ " SGR = R[n]; /* priv mode */",
+ "else",
+ " RAISE_EXCEPTION (SIGILL); /* user mode */",
+ },
+ { "", "n", "ldc <REG_N>,TBR", "0100nnnn01001010",
+ "if (SR_MD)", /* FIXME? */
+ " TBR = R[n]; /* priv mode */",
+ "else",
+ " RAISE_EXCEPTION (SIGILL); /* user mode */",
+ },
+ { "n", "n", "ldc.l @<REG_N>+,<CREG_M>", "0100nnnnmmmm0111",
+ "MA (1);",
+ "CREG (m) = RLAT (R[n]);",
+ "R[n] += 4;",
+ "/* FIXME: user mode */",
+ },
+ { "n", "n", "ldc.l @<REG_N>+,SR", "0100nnnn00000111",
+ "MA (1);",
+ "SET_SR (RLAT (R[n]));",
+ "R[n] += 4;",
+ "/* FIXME: user mode */",
+ },
+ { "n", "n", "ldc.l @<REG_N>+,MOD", "0100nnnn01010111",
+ "MA (1);",
+ "SET_MOD (RLAT (R[n]));",
+ "R[n] += 4;",
+ },
+ { "n", "n", "ldc.l @<REG_N>+,DBR", "0100nnnn11110110",
+ "if (SR_MD)",
+ "{ /* priv mode */",
+ " MA (1);",
+ " DBR = RLAT (R[n]);",
+ " R[n] += 4;",
+ "}",
+ "else",
+ " RAISE_EXCEPTION (SIGILL); /* user mode */",
+ },
+ { "n", "n", "ldc.l @<REG_N>+,SGR", "0100nnnn00110110",
+ "if (SR_MD)",
+ "{ /* priv mode */",
+ " MA (1);",
+ " SGR = RLAT (R[n]);",
+ " R[n] += 4;",
+ "}",
+ "else",
+ " RAISE_EXCEPTION (SIGILL); /* user mode */",
+ },
+
+ /* sh-dsp */
+ { "", "", "ldre @(<disp>,PC)", "10001110i8p1....",
+ "RE = SEXT (i) * 2 + 4 + PH2T (PC);",
+ },
+ { "", "", "ldrs @(<disp>,PC)", "10001100i8p1....",
+ "RS = SEXT (i) * 2 + 4 + PH2T (PC);",
+ },
+
+ /* sh4a */
+ { "", "n", "ldrc <REG_N>", "0100nnnn00110100",
+ "SET_RC (R[n]);",
+ "loop = get_loop_bounds_ext (RS, RE, memory, mem_end, maskw, endianw);",
+ "CHECK_INSN_PTR (insn_ptr);",
+ "RE |= 1;",
+ },
+ { "", "", "ldrc #<imm>", "10001010i8*1....",
+ "SET_RC (i);",
+ "loop = get_loop_bounds_ext (RS, RE, memory, mem_end, maskw, endianw);",
+ "CHECK_INSN_PTR (insn_ptr);",
+ "RE |= 1;",
+ },
+
+ { "", "n", "lds <REG_N>,<SREG_M>", "0100nnnnssss1010",
+ "SREG (m) = R[n];",
+ },
+ { "n", "n", "lds.l @<REG_N>+,<SREG_M>", "0100nnnnssss0110",
+ "MA (1);",
+ "SREG (m) = RLAT (R[n]);",
+ "R[n] += 4;",
+ },
+ /* sh2e / sh-dsp (lds <REG_N>,DSR) */
+ { "", "n", "lds <REG_N>,FPSCR", "0100nnnn01101010",
+ "SET_FPSCR (R[n]);",
+ },
+ /* sh2e / sh-dsp (lds.l @<REG_N>+,DSR) */
+ { "n", "n", "lds.l @<REG_N>+,FPSCR", "0100nnnn01100110",
+ "MA (1);",
+ "SET_FPSCR (RLAT (R[n]));",
+ "R[n] += 4;",
+ },
+
+ { "", "", "ldtlb", "0000000000111000",
+ "/* We don't implement cache or tlb, so this is a noop. */",
+ },
+
+ { "nm", "nm", "mac.l @<REG_M>+,@<REG_N>+", "0000nnnnmmmm1111",
+ "macl (&R0, memory, n, m);",
+ },
+
+ { "nm", "nm", "mac.w @<REG_M>+,@<REG_N>+", "0100nnnnmmmm1111",
+ "macw (&R0, memory, n, m, endianw);",
+ },
+
+ { "n", "", "mov #<imm>,<REG_N>", "1110nnnni8*1....",
+ "R[n] = SEXT (i);",
+ },
+ { "n", "", "movi20 #<imm20>,<REG_N>", "0000nnnni8*10000",
+ "RAISE_EXCEPTION_IF_IN_DELAY_SLOT ();",
+ "R[n] = ((i << 24) >> 12) | RIAT (nip);",
+ "SET_NIP (nip + 2); /* Consume 2 more bytes. */",
+ },
+ { "n", "", "movi20s #<imm20>,<REG_N>", "0000nnnni8*10001",
+ "RAISE_EXCEPTION_IF_IN_DELAY_SLOT ();",
+ "R[n] = ((((i & 0xf0) << 24) >> 12) | RIAT (nip)) << 8;",
+ "SET_NIP (nip + 2); /* Consume 2 more bytes. */",
+ },
+ { "n", "m", "mov <REG_M>,<REG_N>", "0110nnnnmmmm0011",
+ "R[n] = R[m];",
+ },
+
+ { "0", "", "mov.b @(<disp>,GBR),R0", "11000100i8*1....",
+ "MA (1);",
+ "R0 = RSBAT (i + GBR);",
+ "L (0);",
+ },
+ { "0", "m", "mov.b @(<disp>,<REG_M>),R0", "10000100mmmmi4*1",
+ "MA (1);",
+ "R0 = RSBAT (i + R[m]);",
+ "L (0);",
+ },
+ { "n", "0m", "mov.b @(R0,<REG_M>),<REG_N>", "0000nnnnmmmm1100",
+ "MA (1);",
+ "R[n] = RSBAT (R0 + R[m]);",
+ "L (n);",
+ },
+ { "nm", "m", "mov.b @<REG_M>+,<REG_N>", "0110nnnnmmmm0100",
+ "MA (1);",
+ "R[n] = RSBAT (R[m]);",
+ "R[m] += 1;",
+ "L (n);",
+ },
+ { "0n", "n", "mov.b @-<REG_N>,R0", "0100nnnn11001011",
+ "MA (1);",
+ "R[n] -= 1;",
+ "R0 = RSBAT (R[n]);",
+ "L (0);",
+ },
+ { "", "mn", "mov.b <REG_M>,@<REG_N>", "0010nnnnmmmm0000",
+ "MA (1);",
+ "WBAT (R[n], R[m]);",
+ },
+ { "", "0", "mov.b R0,@(<disp>,GBR)", "11000000i8*1....",
+ "MA (1);",
+ "WBAT (i + GBR, R0);",
+ },
+ { "", "m0", "mov.b R0,@(<disp>,<REG_M>)", "10000000mmmmi4*1",
+ "MA (1);",
+ "WBAT (i + R[m], R0);",
+ },
+ { "", "mn0", "mov.b <REG_M>,@(R0,<REG_N>)", "0000nnnnmmmm0100",
+ "MA (1);",
+ "WBAT (R[n] + R0, R[m]);",
+ },
+ { "n", "nm", "mov.b <REG_M>,@-<REG_N>", "0010nnnnmmmm0100",
+ /* Allow for the case where m == n. */
+ "int t = R[m];",
+ "MA (1);",
+ "R[n] -= 1;",
+ "WBAT (R[n], t);",
+ },
+ { "n", "n0", "mov.b R0,@<REG_N>+", "0100nnnn10001011",
+ "MA (1);",
+ "WBAT (R[n], R0);",
+ "R[n] += 1;",
+ },
+ { "n", "m", "mov.b @<REG_M>,<REG_N>", "0110nnnnmmmm0000",
+ "MA (1);",
+ "R[n] = RSBAT (R[m]);",
+ "L (n);",
+ },
+
+ { "0", "", "mov.l @(<disp>,GBR),R0", "11000110i8*4....",
+ "MA (1);",
+ "R0 = RLAT (i + GBR);",
+ "L (0);",
+ },
+ { "n", "", "mov.l @(<disp>,PC),<REG_N>", "1101nnnni8p4....",
+ "RAISE_EXCEPTION_IF_IN_DELAY_SLOT ();",
+ "MA (1);",
+ "R[n] = RLAT ((PH2T (PC) & ~3) + 4 + i);",
+ "L (n);",
+ },
+ { "n", "m", "mov.l @(<disp>,<REG_M>),<REG_N>", "0101nnnnmmmmi4*4",
+ "MA (1);",
+ "R[n] = RLAT (i + R[m]);",
+ "L (n);",
+ },
+ { "n", "m0", "mov.l @(R0,<REG_M>),<REG_N>", "0000nnnnmmmm1110",
+ "MA (1);",
+ "R[n] = RLAT (R0 + R[m]);",
+ "L (n);",
+ },
+ { "nm", "m", "mov.l @<REG_M>+,<REG_N>", "0110nnnnmmmm0110",
+ "MA (1);",
+ "R[n] = RLAT (R[m]);",
+ "R[m] += 4;",
+ "L (n);",
+ },
+ { "0n", "n", "mov.l @-<REG_N>,R0", "0100nnnn11101011",
+ "MA (1);",
+ "R[n] -= 4;",
+ "R0 = RLAT (R[n]);",
+ "L (0);",
+ },
+ { "n", "m", "mov.l @<REG_M>,<REG_N>", "0110nnnnmmmm0010",
+ "MA (1);",
+ "R[n] = RLAT (R[m]);",
+ "L (n);",
+ },
+ { "", "0", "mov.l R0,@(<disp>,GBR)", "11000010i8*4....",
+ "MA (1);",
+ "WLAT (i + GBR, R0);",
+ },
+ { "", "nm", "mov.l <REG_M>,@(<disp>,<REG_N>)", "0001nnnnmmmmi4*4",
+ "MA (1);",
+ "WLAT (i + R[n], R[m]);",
+ },
+ { "", "nm0", "mov.l <REG_M>,@(R0,<REG_N>)", "0000nnnnmmmm0110",
+ "MA (1);",
+ "WLAT (R0 + R[n], R[m]);",
+ },
+ { "n", "nm", "mov.l <REG_M>,@-<REG_N>", "0010nnnnmmmm0110",
+ /* Allow for the case where m == n. */
+ "int t = R[m];",
+ "MA (1) ;",
+ "R[n] -= 4;",
+ "WLAT (R[n], t);",
+ },
+ { "n", "n0", "mov.l R0,@<REG_N>+", "0100nnnn10101011",
+ "MA (1) ;",
+ "WLAT (R[n], R0);",
+ "R[n] += 4;",
+ },
+ { "", "nm", "mov.l <REG_M>,@<REG_N>", "0010nnnnmmmm0010",
+ "MA (1);",
+ "WLAT (R[n], R[m]);",
+ },
+
+ { "0", "", "mov.w @(<disp>,GBR),R0", "11000101i8*2....",
+ "MA (1);",
+ "R0 = RSWAT (i + GBR);",
+ "L (0);",
+ },
+ { "n", "", "mov.w @(<disp>,PC),<REG_N>", "1001nnnni8p2....",
+ "RAISE_EXCEPTION_IF_IN_DELAY_SLOT ();",
+ "MA (1);",
+ "R[n] = RSWAT (PH2T (PC + 4 + i));",
+ "L (n);",
+ },
+ { "0", "m", "mov.w @(<disp>,<REG_M>),R0", "10000101mmmmi4*2",
+ "MA (1);",
+ "R0 = RSWAT (i + R[m]);",
+ "L (0);",
+ },
+ { "n", "m0", "mov.w @(R0,<REG_M>),<REG_N>", "0000nnnnmmmm1101",
+ "MA (1);",
+ "R[n] = RSWAT (R0 + R[m]);",
+ "L (n);",
+ },
+ { "nm", "n", "mov.w @<REG_M>+,<REG_N>", "0110nnnnmmmm0101",
+ "MA (1);",
+ "R[n] = RSWAT (R[m]);",
+ "R[m] += 2;",
+ "L (n);",
+ },
+ { "0n", "n", "mov.w @-<REG_N>,R0", "0100nnnn11011011",
+ "MA (1);",
+ "R[n] -= 2;",
+ "R0 = RSWAT (R[n]);",
+ "L (0);",
+ },
+ { "n", "m", "mov.w @<REG_M>,<REG_N>", "0110nnnnmmmm0001",
+ "MA (1);",
+ "R[n] = RSWAT (R[m]);",
+ "L (n);",
+ },
+ { "", "0", "mov.w R0,@(<disp>,GBR)", "11000001i8*2....",
+ "MA (1);",
+ "WWAT (i + GBR, R0);",
+ },
+ { "", "0m", "mov.w R0,@(<disp>,<REG_M>)", "10000001mmmmi4*2",
+ "MA (1);",
+ "WWAT (i + R[m], R0);",
+ },
+ { "", "m0n", "mov.w <REG_M>,@(R0,<REG_N>)", "0000nnnnmmmm0101",
+ "MA (1);",
+ "WWAT (R0 + R[n], R[m]);",
+ },
+ { "n", "mn", "mov.w <REG_M>,@-<REG_N>", "0010nnnnmmmm0101",
+ /* Allow for the case where m == n. */
+ "int t = R[m];",
+ "MA (1);",
+ "R[n] -= 2;",
+ "WWAT (R[n], t);",
+ },
+ { "n", "0n", "mov.w R0,@<REG_N>+", "0100nnnn10011011",
+ "MA (1);",
+ "WWAT (R[n], R0);",
+ "R[n] += 2;",
+ },
+ { "", "nm", "mov.w <REG_M>,@<REG_N>", "0010nnnnmmmm0001",
+ "MA (1);",
+ "WWAT (R[n], R[m]);",
+ },
+
+ { "0", "", "mova @(<disp>,PC),R0", "11000111i8p4....",
+ "RAISE_EXCEPTION_IF_IN_DELAY_SLOT ();",
+ "R0 = ((i + 4 + PH2T (PC)) & ~0x3);",
+ },
+
+ { "", "n0", "movca.l R0, @<REG_N>", "0000nnnn11000011",
+ "/* We don't simulate cache, so this insn is identical to mov. */",
+ "MA (1);",
+ "WLAT (R[n], R[0]);",
+ },
+
+ { "", "n0", "movco.l R0, @<REG_N>", "0000nnnn01110011",
+ "/* LDST -> T */",
+ "SET_SR_T (LDST);",
+ "/* if (T) R0 -> (Rn) */",
+ "if (T)",
+ " WLAT (R[n], R[0]);",
+ "/* 0 -> LDST */",
+ "SET_LDST (0);",
+ },
+
+ { "0", "n", "movli.l @<REG_N>, R0", "0000nnnn01100011",
+ "/* 1 -> LDST */",
+ "SET_LDST (1);",
+ "/* (Rn) -> R0 */",
+ "R[0] = RLAT (R[n]);",
+ "/* if (interrupt/exception) 0 -> LDST */",
+ "/* (we don't simulate asynchronous interrupts/exceptions) */",
+ },
+
+ { "n", "", "movt <REG_N>", "0000nnnn00101001",
+ "R[n] = T;",
+ },
+ { "", "", "movrt <REG_N>", "0000nnnn00111001",
+ "R[n] = (T == 0);",
+ },
+ { "0", "n", "movua.l @<REG_N>,R0", "0100nnnn10101001",
+ "int regn = R[n];",
+ "int e = target_little_endian ? 3 : 0;",
+ "MA (1);",
+ "R[0] = (RBAT (regn + (0^e)) << 24) + (RBAT (regn + (1^e)) << 16) + ",
+ " (RBAT (regn + (2^e)) << 8) + RBAT (regn + (3^e));",
+ "L (0);",
+ },
+ { "0n", "n", "movua.l @<REG_N>+,R0", "0100nnnn11101001",
+ "int regn = R[n];",
+ "int e = target_little_endian ? 3 : 0;",
+ "MA (1);",
+ "R[0] = (RBAT (regn + (0^e)) << 24) + (RBAT (regn + (1^e)) << 16) + ",
+ " (RBAT (regn + (2^e)) << 8) + RBAT (regn + (3^e));",
+ "R[n] += 4;",
+ "L (0);",
+ },
+ { "", "mn", "mul.l <REG_M>,<REG_N>", "0000nnnnmmmm0111",
+ "MACL = ((int) R[n]) * ((int) R[m]);",
+ },
+#if 0 /* FIXME: The above cast to int is not really portable.
+ It should be replaced by a SEXT32 macro. */
+ { "", "nm", "mul.l <REG_M>,<REG_N>", "0000nnnnmmmm0111",
+ "MACL = R[n] * R[m];",
+ },
+#endif
+
+ /* muls.w - see muls */
+ { "", "mn", "muls <REG_M>,<REG_N>", "0010nnnnmmmm1111",
+ "MACL = ((int) (short) R[n]) * ((int) (short) R[m]);",
+ },
+
+ /* mulu.w - see mulu */
+ { "", "mn", "mulu <REG_M>,<REG_N>", "0010nnnnmmmm1110",
+ "MACL = (((unsigned int) (unsigned short) R[n])",
+ " * ((unsigned int) (unsigned short) R[m]));",
+ },
+
+ { "n", "m", "neg <REG_M>,<REG_N>", "0110nnnnmmmm1011",
+ "R[n] = - R[m];",
+ },
+
+ { "n", "m", "negc <REG_M>,<REG_N>", "0110nnnnmmmm1010",
+ "ult = -T;",
+ "SET_SR_T (ult > 0);",
+ "R[n] = ult - R[m];",
+ "SET_SR_T (T || (R[n] > ult));",
+ },
+
+ { "", "", "nop", "0000000000001001",
+ "/* nop */",
+ },
+
+ { "n", "m", "not <REG_M>,<REG_N>", "0110nnnnmmmm0111",
+ "R[n] = ~R[m];",
+ },
+
+ /* sh4a */
+ { "", "n", "icbi @<REG_N>", "0000nnnn11100011",
+ "/* Except for the effect on the cache - which is not simulated -",
+ " this is like a nop. */",
+ },
+
+ { "", "n", "ocbi @<REG_N>", "0000nnnn10010011",
+ "RSBAT (R[n]); /* Take exceptions like byte load, otherwise noop. */",
+ "/* FIXME: Cache not implemented */",
+ },
+
+ { "", "n", "ocbp @<REG_N>", "0000nnnn10100011",
+ "RSBAT (R[n]); /* Take exceptions like byte load, otherwise noop. */",
+ "/* FIXME: Cache not implemented */",
+ },
+
+ { "", "n", "ocbwb @<REG_N>", "0000nnnn10110011",
+ "RSBAT (R[n]); /* Take exceptions like byte load, otherwise noop. */",
+ "/* FIXME: Cache not implemented */",
+ },
+
+ { "0", "", "or #<imm>,R0", "11001011i8*1....",
+ "R0 |= i;",
+ },
+ { "n", "m", "or <REG_M>,<REG_N>", "0010nnnnmmmm1011",
+ "R[n] |= R[m];",
+ },
+ { "", "0", "or.b #<imm>,@(R0,GBR)", "11001111i8*1....",
+ "MA (1);",
+ "WBAT (R0 + GBR, (RBAT (R0 + GBR) | i));",
+ },
+
+ { "", "n", "pref @<REG_N>", "0000nnnn10000011",
+ "/* Except for the effect on the cache - which is not simulated -",
+ " this is like a nop. */",
+ },
+
+ /* sh4a */
+ { "", "n", "prefi @<REG_N>", "0000nnnn11010011",
+ "/* Except for the effect on the cache - which is not simulated -",
+ " this is like a nop. */",
+ },
+
+ /* sh4a */
+ { "", "", "synco", "0000000010101011",
+ "/* Except for the effect on the pipeline - which is not simulated -",
+ " this is like a nop. */",
+ },
+
+ { "n", "n", "rotcl <REG_N>", "0100nnnn00100100",
+ "ult = R[n] < 0;",
+ "R[n] = (R[n] << 1) | T;",
+ "SET_SR_T (ult);",
+ },
+
+ { "n", "n", "rotcr <REG_N>", "0100nnnn00100101",
+ "ult = R[n] & 1;",
+ "R[n] = (UR[n] >> 1) | (T << 31);",
+ "SET_SR_T (ult);",
+ },
+
+ { "n", "n", "rotl <REG_N>", "0100nnnn00000100",
+ "SET_SR_T (R[n] < 0);",
+ "R[n] <<= 1;",
+ "R[n] |= T;",
+ },
+
+ { "n", "n", "rotr <REG_N>", "0100nnnn00000101",
+ "SET_SR_T (R[n] & 1);",
+ "R[n] = UR[n] >> 1;",
+ "R[n] |= (T << 31);",
+ },
+
+ { "", "", "rte", "0000000000101011",
+#if 0
+ /* SH-[12] */
+ "int tmp = PC;",
+ "SET_NIP (PT2H (RLAT (R[15]) + 2));",
+ "R[15] += 4;",
+ "SET_SR (RLAT (R[15]) & 0x3f3);",
+ "R[15] += 4;",
+ "Delay_Slot (PC + 2);",
+#else
+ "RAISE_EXCEPTION_IF_IN_DELAY_SLOT ();",
+ "SET_SR (SSR);",
+ "SET_NIP (PT2H (SPC));",
+ "cycles += 2;",
+ "Delay_Slot (PC + 2);",
+#endif
+ },
+
+ { "", "", "rts", "0000000000001011",
+ "RAISE_EXCEPTION_IF_IN_DELAY_SLOT ();",
+ "SET_NIP (PT2H (PR));",
+ "cycles += 2;",
+ "Delay_Slot (PC + 2);",
+ },
+ { "", "", "rts/n", "0000000001101011",
+ "RAISE_EXCEPTION_IF_IN_DELAY_SLOT ();",
+ "SET_NIP (PT2H (PR));",
+ },
+ { "0", "n", "rtv/n <REG_N>", "0000nnnn01111011",
+ "RAISE_EXCEPTION_IF_IN_DELAY_SLOT ();",
+ "R0 = R[n];",
+ "L (0);",
+ "SET_NIP (PT2H (PR));",
+ },
+
+ /* sh4a */
+ { "", "", "setdmx", "0000000010011000",
+ "saved_state.asregs.cregs.named.sr |= SR_MASK_DMX;"
+ "saved_state.asregs.cregs.named.sr &= ~SR_MASK_DMY;"
+ },
+
+ /* sh4a */
+ { "", "", "setdmy", "0000000011001000",
+ "saved_state.asregs.cregs.named.sr |= SR_MASK_DMY;"
+ "saved_state.asregs.cregs.named.sr &= ~SR_MASK_DMX;"
+ },
+
+ /* sh-dsp */
+ { "", "n", "setrc <REG_N>", "0100nnnn00010100",
+ "SET_RC (R[n]);",
+ },
+ { "", "", "setrc #<imm>", "10000010i8*1....",
+ /* It would be more realistic to let loop_start point to some static
+ memory that contains an illegal opcode and then give a bus error when
+ the loop is eventually encountered, but it seems not only simpler,
+ but also more debugging-friendly to just catch the failure here. */
+ "if (BUSERROR (RS | RE, maskw))",
+ " RAISE_EXCEPTION (SIGILL);",
+ "else {",
+ " SET_RC (i);",
+ " loop = get_loop_bounds (RS, RE, memory, mem_end, maskw, endianw);",
+ " CHECK_INSN_PTR (insn_ptr);",
+ "}",
+ },
+
+ { "", "", "sets", "0000000001011000",
+ "SET_SR_S (1);",
+ },
+
+ { "", "", "sett", "0000000000011000",
+ "SET_SR_T (1);",
+ },
+
+ { "n", "mn", "shad <REG_M>,<REG_N>", "0100nnnnmmmm1100",
+ "R[n] = (R[m] < 0) ? (R[m]&0x1f ? R[n] >> ((-R[m])&0x1f) : R[n] >> 31) : (R[n] << (R[m] & 0x1f));",
+ },
+
+ { "n", "n", "shal <REG_N>", "0100nnnn00100000",
+ "SET_SR_T (R[n] < 0);",
+ "R[n] <<= 1;",
+ },
+
+ { "n", "n", "shar <REG_N>", "0100nnnn00100001",
+ "SET_SR_T (R[n] & 1);",
+ "R[n] = R[n] >> 1;",
+ },
+
+ { "n", "mn", "shld <REG_M>,<REG_N>", "0100nnnnmmmm1101",
+ "R[n] = (R[m] < 0) ? (R[m]&0x1f ? UR[n] >> ((-R[m])&0x1f) : 0): (R[n] << (R[m] & 0x1f));",
+ },
+
+ { "n", "n", "shll <REG_N>", "0100nnnn00000000",
+ "SET_SR_T (R[n] < 0);",
+ "R[n] <<= 1;",
+ },
+
+ { "n", "n", "shll2 <REG_N>", "0100nnnn00001000",
+ "R[n] <<= 2;",
+ },
+ { "n", "n", "shll8 <REG_N>", "0100nnnn00011000",
+ "R[n] <<= 8;",
+ },
+ { "n", "n", "shll16 <REG_N>", "0100nnnn00101000",
+ "R[n] <<= 16;",
+ },
+
+ { "n", "n", "shlr <REG_N>", "0100nnnn00000001",
+ "SET_SR_T (R[n] & 1);",
+ "R[n] = UR[n] >> 1;",
+ },
+
+ { "n", "n", "shlr2 <REG_N>", "0100nnnn00001001",
+ "R[n] = UR[n] >> 2;",
+ },
+ { "n", "n", "shlr8 <REG_N>", "0100nnnn00011001",
+ "R[n] = UR[n] >> 8;",
+ },
+ { "n", "n", "shlr16 <REG_N>", "0100nnnn00101001",
+ "R[n] = UR[n] >> 16;",
+ },
+
+ { "", "", "sleep", "0000000000011011",
+ "nip += trap (sd, 0xc3, &R0, PC, memory, maskl, maskw, endianw);",
+ },
+
+ { "n", "", "stc <CREG_M>,<REG_N>", "0000nnnnmmmm0010",
+ "R[n] = CREG (m);",
+ },
+
+ { "n", "", "stc SGR,<REG_N>", "0000nnnn00111010",
+ "if (SR_MD)",
+ " R[n] = SGR; /* priv mode */",
+ "else",
+ " RAISE_EXCEPTION (SIGILL); /* user mode */",
+ },
+ { "n", "", "stc DBR,<REG_N>", "0000nnnn11111010",
+ "if (SR_MD)",
+ " R[n] = DBR; /* priv mode */",
+ "else",
+ " RAISE_EXCEPTION (SIGILL); /* user mode */",
+ },
+ { "n", "", "stc TBR,<REG_N>", "0000nnnn01001010",
+ "if (SR_MD)", /* FIXME? */
+ " R[n] = TBR; /* priv mode */",
+ "else",
+ " RAISE_EXCEPTION (SIGILL); /* user mode */",
+ },
+ { "n", "n", "stc.l <CREG_M>,@-<REG_N>", "0100nnnnmmmm0011",
+ "MA (1);",
+ "R[n] -= 4;",
+ "WLAT (R[n], CREG (m));",
+ },
+ { "n", "n", "stc.l SGR,@-<REG_N>", "0100nnnn00110010",
+ "if (SR_MD)",
+ "{ /* priv mode */",
+ " MA (1);",
+ " R[n] -= 4;",
+ " WLAT (R[n], SGR);",
+ "}",
+ "else",
+ " RAISE_EXCEPTION (SIGILL); /* user mode */",
+ },
+ { "n", "n", "stc.l DBR,@-<REG_N>", "0100nnnn11110010",
+ "if (SR_MD)",
+ "{ /* priv mode */",
+ " MA (1);",
+ " R[n] -= 4;",
+ " WLAT (R[n], DBR);",
+ "}",
+ "else",
+ " RAISE_EXCEPTION (SIGILL); /* user mode */",
+ },
+
+ { "n", "", "sts <SREG_M>,<REG_N>", "0000nnnnssss1010",
+ "R[n] = SREG (m);",
+ },
+ { "n", "n", "sts.l <SREG_M>,@-<REG_N>", "0100nnnnssss0010",
+ "MA (1);",
+ "R[n] -= 4;",
+ "WLAT (R[n], SREG (m));",
+ },
+
+ { "n", "nm", "sub <REG_M>,<REG_N>", "0011nnnnmmmm1000",
+ "R[n] -= R[m];",
+ },
+
+ { "n", "nm", "subc <REG_M>,<REG_N>", "0011nnnnmmmm1010",
+ "ult = R[n] - T;",
+ "SET_SR_T (ult > R[n]);",
+ "R[n] = ult - R[m];",
+ "SET_SR_T (T || (R[n] > ult));",
+ },
+
+ { "n", "nm", "subv <REG_M>,<REG_N>", "0011nnnnmmmm1011",
+ "ult = R[n] - R[m];",
+ "SET_SR_T (((R[n] ^ R[m]) & (ult ^ R[n])) >> 31);",
+ "R[n] = ult;",
+ },
+
+ { "n", "nm", "swap.b <REG_M>,<REG_N>", "0110nnnnmmmm1000",
+ "R[n] = ((R[m] & 0xffff0000)",
+ " | ((R[m] << 8) & 0xff00)",
+ " | ((R[m] >> 8) & 0x00ff));",
+ },
+ { "n", "nm", "swap.w <REG_M>,<REG_N>", "0110nnnnmmmm1001",
+ "R[n] = (((R[m] << 16) & 0xffff0000)",
+ " | ((R[m] >> 16) & 0x00ffff));",
+ },
+
+ { "", "n", "tas.b @<REG_N>", "0100nnnn00011011",
+ "MA (1);",
+ "ult = RBAT (R[n]);",
+ "SET_SR_T (ult == 0);",
+ "WBAT (R[n],ult|0x80);",
+ },
+
+ { "0", "", "trapa #<imm>", "11000011i8*1....",
+ "long imm = 0xff & i;",
+ "RAISE_EXCEPTION_IF_IN_DELAY_SLOT ();",
+ "if (i < 20 || i == 33 || i == 34 || i == 0xc3)",
+ " nip += trap (sd, i, &R0, PC, memory, maskl, maskw, endianw);",
+#if 0
+ "else {",
+ /* SH-[12] */
+ " R[15] -= 4;",
+ " WLAT (R[15], GET_SR ());",
+ " R[15] -= 4;",
+ " WLAT (R[15], PH2T (PC + 2));",
+#else
+ "else if (!SR_BL) {",
+ " SSR = GET_SR ();",
+ " SPC = PH2T (PC + 2);",
+ " SET_SR (GET_SR () | SR_MASK_MD | SR_MASK_BL | SR_MASK_RB);",
+ " /* FIXME: EXPEVT = 0x00000160; */",
+#endif
+ " SET_NIP (PT2H (RLAT (VBR + (imm<<2))));",
+ "}",
+ },
+
+ { "", "mn", "tst <REG_M>,<REG_N>", "0010nnnnmmmm1000",
+ "SET_SR_T ((R[n] & R[m]) == 0);",
+ },
+ { "", "0", "tst #<imm>,R0", "11001000i8*1....",
+ "SET_SR_T ((R0 & i) == 0);",
+ },
+ { "", "0", "tst.b #<imm>,@(R0,GBR)", "11001100i8*1....",
+ "MA (1);",
+ "SET_SR_T ((RBAT (GBR+R0) & i) == 0);",
+ },
+
+ { "", "0", "xor #<imm>,R0", "11001010i8*1....",
+ "R0 ^= i;",
+ },
+ { "n", "mn", "xor <REG_M>,<REG_N>", "0010nnnnmmmm1010",
+ "R[n] ^= R[m];",
+ },
+ { "", "0", "xor.b #<imm>,@(R0,GBR)", "11001110i8*1....",
+ "MA (1);",
+ "ult = RBAT (GBR+R0);",
+ "ult ^= i;",
+ "WBAT (GBR + R0, ult);",
+ },
+
+ { "n", "nm", "xtrct <REG_M>,<REG_N>", "0010nnnnmmmm1101",
+ "R[n] = (((R[n] >> 16) & 0xffff)",
+ " | ((R[m] << 16) & 0xffff0000));",
+ },