+#define CREG(n) (saved_state.asregs.cregs.i[(n)])
+#define GBR saved_state.asregs.cregs.named.gbr
+#define VBR saved_state.asregs.cregs.named.vbr
+#define DBR saved_state.asregs.cregs.named.dbr
+#define TBR saved_state.asregs.cregs.named.tbr
+#define IBCR saved_state.asregs.cregs.named.ibcr
+#define IBNR saved_state.asregs.cregs.named.ibnr
+#define BANKN (saved_state.asregs.cregs.named.ibnr & 0x1ff)
+#define ME ((saved_state.asregs.cregs.named.ibnr >> 14) & 0x3)
+#define SSR saved_state.asregs.cregs.named.ssr
+#define SPC saved_state.asregs.cregs.named.spc
+#define SGR saved_state.asregs.cregs.named.sgr
+#define SREG(n) (saved_state.asregs.sregs.i[(n)])
+#define MACH saved_state.asregs.sregs.named.mach
+#define MACL saved_state.asregs.sregs.named.macl
+#define PR saved_state.asregs.sregs.named.pr
+#define FPUL saved_state.asregs.sregs.named.fpul
+
+#define PC insn_ptr
+
+
+
+/* Alternate bank of registers r0-r7 */
+
+/* Note: code controling SR handles flips between BANK0 and BANK1 */
+#define Rn_BANK(n) (saved_state.asregs.cregs.named.bank[(n)])
+#define SET_Rn_BANK(n, EXP) do { saved_state.asregs.cregs.named.bank[(n)] = (EXP); } while (0)
+
+
+/* Manipulate SR */
+
+#define SR_MASK_BO (1 << 14)
+#define SR_MASK_CS (1 << 13)
+#define SR_MASK_DMY (1 << 11)
+#define SR_MASK_DMX (1 << 10)
+#define SR_MASK_M (1 << 9)
+#define SR_MASK_Q (1 << 8)
+#define SR_MASK_I (0xf << 4)
+#define SR_MASK_S (1 << 1)
+#define SR_MASK_T (1 << 0)
+
+#define SR_MASK_BL (1 << 28)
+#define SR_MASK_RB (1 << 29)
+#define SR_MASK_MD (1 << 30)
+#define SR_MASK_RC 0x0fff0000
+#define SR_RC_INCREMENT -0x00010000
+
+#define BO ((saved_state.asregs.cregs.named.sr & SR_MASK_BO) != 0)
+#define CS ((saved_state.asregs.cregs.named.sr & SR_MASK_CS) != 0)
+#define M ((saved_state.asregs.cregs.named.sr & SR_MASK_M) != 0)
+#define Q ((saved_state.asregs.cregs.named.sr & SR_MASK_Q) != 0)
+#define S ((saved_state.asregs.cregs.named.sr & SR_MASK_S) != 0)
+#define T ((saved_state.asregs.cregs.named.sr & SR_MASK_T) != 0)
+#define LDST ((saved_state.asregs.cregs.named.ldst) != 0)
+
+#define SR_BL ((saved_state.asregs.cregs.named.sr & SR_MASK_BL) != 0)
+#define SR_RB ((saved_state.asregs.cregs.named.sr & SR_MASK_RB) != 0)
+#define SR_MD ((saved_state.asregs.cregs.named.sr & SR_MASK_MD) != 0)
+#define SR_DMY ((saved_state.asregs.cregs.named.sr & SR_MASK_DMY) != 0)
+#define SR_DMX ((saved_state.asregs.cregs.named.sr & SR_MASK_DMX) != 0)
+#define SR_RC ((saved_state.asregs.cregs.named.sr & SR_MASK_RC))
+
+/* Note: don't use this for privileged bits */
+#define SET_SR_BIT(EXP, BIT) \
+do { \
+ if ((EXP) & 1) \
+ saved_state.asregs.cregs.named.sr |= (BIT); \
+ else \
+ saved_state.asregs.cregs.named.sr &= ~(BIT); \
+} while (0)
+
+#define SET_SR_BO(EXP) SET_SR_BIT ((EXP), SR_MASK_BO)
+#define SET_SR_CS(EXP) SET_SR_BIT ((EXP), SR_MASK_CS)
+#define SET_BANKN(EXP) \
+do { \
+ IBNR = (IBNR & 0xfe00) | (EXP & 0x1f); \
+} while (0)
+#define SET_ME(EXP) \
+do { \
+ IBNR = (IBNR & 0x3fff) | ((EXP & 0x3) << 14); \
+} while (0)
+#define SET_SR_M(EXP) SET_SR_BIT ((EXP), SR_MASK_M)
+#define SET_SR_Q(EXP) SET_SR_BIT ((EXP), SR_MASK_Q)
+#define SET_SR_S(EXP) SET_SR_BIT ((EXP), SR_MASK_S)
+#define SET_SR_T(EXP) SET_SR_BIT ((EXP), SR_MASK_T)
+#define SET_LDST(EXP) (saved_state.asregs.cregs.named.ldst = ((EXP) != 0))
+
+/* stc currently relies on being able to read SR without modifications. */
+#define GET_SR() (saved_state.asregs.cregs.named.sr - 0)
+
+#define SET_SR(x) set_sr (x)
+
+#define SET_RC(x) \
+ (saved_state.asregs.cregs.named.sr \
+ = saved_state.asregs.cregs.named.sr & 0xf000ffff | ((x) & 0xfff) << 16)
+
+/* Manipulate FPSCR */
+
+#define FPSCR_MASK_FR (1 << 21)
+#define FPSCR_MASK_SZ (1 << 20)
+#define FPSCR_MASK_PR (1 << 19)
+
+#define FPSCR_FR ((GET_FPSCR () & FPSCR_MASK_FR) != 0)
+#define FPSCR_SZ ((GET_FPSCR () & FPSCR_MASK_SZ) != 0)
+#define FPSCR_PR ((GET_FPSCR () & FPSCR_MASK_PR) != 0)
+
+/* Count the number of arguments in an argv. */
+static int
+count_argc (char **argv)
+{
+ int i;
+
+ if (! argv)
+ return -1;
+
+ for (i = 0; argv[i] != NULL; ++i)
+ continue;
+ return i;
+}
+
+static void
+set_fpscr1 (int x)
+{
+ int old = saved_state.asregs.sregs.named.fpscr;
+ saved_state.asregs.sregs.named.fpscr = (x);
+ /* swap the floating point register banks */
+ if ((saved_state.asregs.sregs.named.fpscr ^ old) & FPSCR_MASK_FR
+ /* Ignore bit change if simulating sh-dsp. */
+ && ! target_dsp)
+ {
+ union fregs_u tmpf = saved_state.asregs.fregs[0];
+ saved_state.asregs.fregs[0] = saved_state.asregs.fregs[1];
+ saved_state.asregs.fregs[1] = tmpf;
+ }
+}
+
+/* sts relies on being able to read fpscr directly. */
+#define GET_FPSCR() (saved_state.asregs.sregs.named.fpscr)
+#define SET_FPSCR(x) \
+do { \
+ set_fpscr1 (x); \
+} while (0)