+ fprintf (stderr,
+ "Not enough VM for simulation of %d bytes of RAM\n",
+ saved_state.asregs.msize);
+
+ saved_state.asregs.msize = 1;
+ saved_state.asregs.memory = (unsigned char *) mcalloc (1, 1);
+ }
+}
+
+static void
+init_dsp (struct bfd *abfd)
+{
+ int was_dsp = target_dsp;
+ unsigned long mach = bfd_get_mach (abfd);
+
+ if (mach == bfd_mach_sh_dsp ||
+ mach == bfd_mach_sh4al_dsp ||
+ mach == bfd_mach_sh3_dsp)
+ {
+ int ram_area_size, xram_start, yram_start;
+ int new_select;
+
+ target_dsp = 1;
+ if (mach == bfd_mach_sh_dsp)
+ {
+ /* SH7410 (orig. sh-sdp):
+ 4KB each for X & Y memory;
+ On-chip X RAM 0x0800f000-0x0800ffff
+ On-chip Y RAM 0x0801f000-0x0801ffff */
+ xram_start = 0x0800f000;
+ ram_area_size = 0x1000;
+ }
+ if (mach == bfd_mach_sh3_dsp || mach == bfd_mach_sh4al_dsp)
+ {
+ /* SH7612:
+ 8KB each for X & Y memory;
+ On-chip X RAM 0x1000e000-0x1000ffff
+ On-chip Y RAM 0x1001e000-0x1001ffff */
+ xram_start = 0x1000e000;
+ ram_area_size = 0x2000;
+ }
+ yram_start = xram_start + 0x10000;
+ new_select = ~(ram_area_size - 1);
+ if (saved_state.asregs.xyram_select != new_select)
+ {
+ saved_state.asregs.xyram_select = new_select;
+ free (saved_state.asregs.xmem);
+ free (saved_state.asregs.ymem);
+ saved_state.asregs.xmem =
+ (unsigned char *) calloc (1, ram_area_size);
+ saved_state.asregs.ymem =
+ (unsigned char *) calloc (1, ram_area_size);
+
+ /* Disable use of X / Y mmeory if not allocated. */
+ if (! saved_state.asregs.xmem || ! saved_state.asregs.ymem)
+ {
+ saved_state.asregs.xyram_select = 0;
+ if (saved_state.asregs.xmem)
+ free (saved_state.asregs.xmem);
+ if (saved_state.asregs.ymem)
+ free (saved_state.asregs.ymem);
+ }
+ }
+ saved_state.asregs.xram_start = xram_start;
+ saved_state.asregs.yram_start = yram_start;
+ saved_state.asregs.xmem_offset = saved_state.asregs.xmem - xram_start;
+ saved_state.asregs.ymem_offset = saved_state.asregs.ymem - yram_start;
+ }
+ else
+ {
+ target_dsp = 0;
+ if (saved_state.asregs.xyram_select)
+ {
+ saved_state.asregs.xyram_select = 0;
+ free (saved_state.asregs.xmem);
+ free (saved_state.asregs.ymem);
+ }
+ }
+
+ if (! saved_state.asregs.xyram_select)
+ {
+ saved_state.asregs.xram_start = 1;
+ saved_state.asregs.yram_start = 1;
+ }
+
+ if (saved_state.asregs.regstack == NULL)
+ saved_state.asregs.regstack =
+ calloc (512, sizeof *saved_state.asregs.regstack);
+
+ if (target_dsp != was_dsp)
+ {
+ int i, tmp;
+
+ for (i = ARRAY_SIZE (sh_dsp_table) - 1; i >= 0; i--)
+ {
+ tmp = sh_jump_table[0xf000 + i];
+ sh_jump_table[0xf000 + i] = sh_dsp_table[i];
+ sh_dsp_table[i] = tmp;
+ }
+ }
+}
+
+static void
+init_pointers (void)
+{
+ if (saved_state.asregs.msize != 1 << sim_memory_size)
+ {
+ sim_size (sim_memory_size);
+ }
+
+ if (saved_state.asregs.profile && !profile_file)
+ {
+ profile_file = fopen ("gmon.out", "wb");
+ /* Seek to where to put the call arc data */
+ nsamples = (1 << sim_profile_size);
+
+ fseek (profile_file, nsamples * 2 + 12, 0);
+
+ if (!profile_file)
+ {
+ fprintf (stderr, "Can't open gmon.out\n");
+ }
+ else
+ {
+ saved_state.asregs.profile_hist =
+ (unsigned short *) calloc (64, (nsamples * sizeof (short) / 64));
+ }
+ }
+}
+
+static void
+dump_profile (void)
+{
+ unsigned int minpc;
+ unsigned int maxpc;
+ unsigned short *p;
+ int i;
+
+ p = saved_state.asregs.profile_hist;
+ minpc = 0;
+ maxpc = (1 << sim_profile_size);
+
+ fseek (profile_file, 0L, 0);
+ swapout (minpc << PROFILE_SHIFT);
+ swapout (maxpc << PROFILE_SHIFT);
+ swapout (nsamples * 2 + 12);
+ for (i = 0; i < nsamples; i++)
+ swapout16 (saved_state.asregs.profile_hist[i]);
+
+}
+
+static void
+gotcall (int from, int to)
+{
+ swapout (from);
+ swapout (to);
+ swapout (1);
+}
+
+#define MMASKB ((saved_state.asregs.msize -1) & ~0)
+
+void
+sim_resume (SIM_DESC sd, int step, int siggnal)
+{
+ register unsigned char *insn_ptr;
+ unsigned char *mem_end;
+ struct loop_bounds loop;
+ register int cycles = 0;
+ register int stalls = 0;
+ register int memstalls = 0;
+ register int insts = 0;
+ register int prevlock;
+#if 1
+ int thislock;
+#else
+ register int thislock;
+#endif
+ register unsigned int doprofile;
+ register int pollcount = 0;
+ /* endianw is used for every insn fetch, hence it makes sense to cache it.
+ endianb is used less often. */
+ register int endianw = global_endianw;
+
+ int tick_start = get_now ();
+ void (*prev_fpe) ();
+
+ register unsigned short *jump_table = sh_jump_table;
+
+ register int *R = &(saved_state.asregs.regs[0]);
+ /*register int T;*/
+#ifndef PR
+ register int PR;
+#endif
+
+ register int maskb = ~((saved_state.asregs.msize - 1) & ~0);
+ register int maskw = ~((saved_state.asregs.msize - 1) & ~1);
+ register int maskl = ~((saved_state.asregs.msize - 1) & ~3);
+ register unsigned char *memory;
+ register unsigned int sbit = ((unsigned int) 1 << 31);
+
+ prev_fpe = signal (SIGFPE, SIG_IGN);
+
+ init_pointers ();
+ saved_state.asregs.exception = 0;
+
+ memory = saved_state.asregs.memory;
+ mem_end = memory + saved_state.asregs.msize;
+
+ if (RE & 1)
+ loop = get_loop_bounds_ext (RS, RE, memory, mem_end, maskw, endianw);
+ else
+ loop = get_loop_bounds (RS, RE, memory, mem_end, maskw, endianw);
+
+ insn_ptr = PT2H (saved_state.asregs.pc);
+ CHECK_INSN_PTR (insn_ptr);
+
+#ifndef PR
+ PR = saved_state.asregs.sregs.named.pr;
+#endif
+ /*T = GET_SR () & SR_MASK_T;*/
+ prevlock = saved_state.asregs.prevlock;
+ thislock = saved_state.asregs.thislock;
+ doprofile = saved_state.asregs.profile;
+
+ /* If profiling not enabled, disable it by asking for
+ profiles infrequently. */
+ if (doprofile == 0)
+ doprofile = ~0;
+
+ loop:
+ if (step && insn_ptr < saved_state.asregs.insn_end)
+ {
+ if (saved_state.asregs.exception)
+ /* This can happen if we've already been single-stepping and
+ encountered a loop end. */
+ saved_state.asregs.insn_end = insn_ptr;
+ else
+ {
+ saved_state.asregs.exception = SIGTRAP;
+ saved_state.asregs.insn_end = insn_ptr + 2;
+ }
+ }
+
+ while (insn_ptr < saved_state.asregs.insn_end)
+ {
+ register unsigned int iword = RIAT (insn_ptr);
+ register unsigned int ult;
+ register unsigned char *nip = insn_ptr + 2;
+
+#ifndef ACE_FAST
+ insts++;
+#endif
+ top:
+
+#include "code.c"
+
+
+ in_delay_slot = 0;
+ insn_ptr = nip;
+
+ if (--pollcount < 0)
+ {
+ host_callback *callback = STATE_CALLBACK (sd);
+
+ pollcount = POLL_QUIT_INTERVAL;
+ if ((*callback->poll_quit) != NULL
+ && (*callback->poll_quit) (callback))
+ {
+ sim_stop (sd);
+ }
+ }
+
+#ifndef ACE_FAST
+ prevlock = thislock;
+ thislock = 30;
+ cycles++;
+
+ if (cycles >= doprofile)
+ {
+
+ saved_state.asregs.cycles += doprofile;
+ cycles -= doprofile;
+ if (saved_state.asregs.profile_hist)
+ {
+ int n = PH2T (insn_ptr) >> PROFILE_SHIFT;
+ if (n < nsamples)
+ {
+ int i = saved_state.asregs.profile_hist[n];
+ if (i < 65000)
+ saved_state.asregs.profile_hist[n] = i + 1;
+ }
+
+ }
+ }
+#endif
+ }
+ if (saved_state.asregs.insn_end == loop.end)
+ {
+ saved_state.asregs.cregs.named.sr += SR_RC_INCREMENT;
+ if (SR_RC)
+ insn_ptr = loop.start;
+ else
+ {
+ saved_state.asregs.insn_end = mem_end;
+ loop.end = PT2H (0);
+ }
+ goto loop;
+ }
+
+ if (saved_state.asregs.exception == SIGILL
+ || saved_state.asregs.exception == SIGBUS)
+ {
+ insn_ptr -= 2;
+ }
+ /* Check for SIGBUS due to insn fetch. */
+ else if (! saved_state.asregs.exception)
+ saved_state.asregs.exception = SIGBUS;
+
+ saved_state.asregs.ticks += get_now () - tick_start;
+ saved_state.asregs.cycles += cycles;
+ saved_state.asregs.stalls += stalls;
+ saved_state.asregs.memstalls += memstalls;
+ saved_state.asregs.insts += insts;
+ saved_state.asregs.pc = PH2T (insn_ptr);
+#ifndef PR
+ saved_state.asregs.sregs.named.pr = PR;
+#endif
+
+ saved_state.asregs.prevlock = prevlock;
+ saved_state.asregs.thislock = thislock;
+
+ if (profile_file)
+ {
+ dump_profile ();
+ }
+
+ signal (SIGFPE, prev_fpe);
+}
+
+int
+sim_write (SIM_DESC sd, SIM_ADDR addr, const unsigned char *buffer, int size)
+{
+ int i;
+
+ init_pointers ();
+
+ for (i = 0; i < size; i++)
+ {
+ saved_state.asregs.memory[(MMASKB & (addr + i)) ^ endianb] = buffer[i];
+ }
+ return size;
+}
+
+int
+sim_read (SIM_DESC sd, SIM_ADDR addr, unsigned char *buffer, int size)
+{
+ int i;
+
+ init_pointers ();
+
+ for (i = 0; i < size; i++)
+ {
+ buffer[i] = saved_state.asregs.memory[(MMASKB & (addr + i)) ^ endianb];
+ }
+ return size;
+}
+
+static int gdb_bank_number;
+enum {
+ REGBANK_MACH = 15,
+ REGBANK_IVN = 16,
+ REGBANK_PR = 17,
+ REGBANK_GBR = 18,
+ REGBANK_MACL = 19
+};
+
+static int
+sh_reg_store (SIM_CPU *cpu, int rn, unsigned char *memory, int length)
+{
+ unsigned val;
+
+ init_pointers ();
+ val = swap (* (int *) memory);
+ switch (rn)
+ {
+ case SIM_SH_R0_REGNUM: case SIM_SH_R1_REGNUM: case SIM_SH_R2_REGNUM:
+ case SIM_SH_R3_REGNUM: case SIM_SH_R4_REGNUM: case SIM_SH_R5_REGNUM:
+ case SIM_SH_R6_REGNUM: case SIM_SH_R7_REGNUM: case SIM_SH_R8_REGNUM:
+ case SIM_SH_R9_REGNUM: case SIM_SH_R10_REGNUM: case SIM_SH_R11_REGNUM:
+ case SIM_SH_R12_REGNUM: case SIM_SH_R13_REGNUM: case SIM_SH_R14_REGNUM:
+ case SIM_SH_R15_REGNUM:
+ saved_state.asregs.regs[rn] = val;
+ break;
+ case SIM_SH_PC_REGNUM:
+ saved_state.asregs.pc = val;
+ break;
+ case SIM_SH_PR_REGNUM:
+ PR = val;
+ break;
+ case SIM_SH_GBR_REGNUM:
+ GBR = val;
+ break;
+ case SIM_SH_VBR_REGNUM:
+ VBR = val;
+ break;
+ case SIM_SH_MACH_REGNUM:
+ MACH = val;
+ break;
+ case SIM_SH_MACL_REGNUM:
+ MACL = val;
+ break;
+ case SIM_SH_SR_REGNUM:
+ SET_SR (val);
+ break;
+ case SIM_SH_FPUL_REGNUM:
+ FPUL = val;
+ break;
+ case SIM_SH_FPSCR_REGNUM:
+ SET_FPSCR (val);
+ break;
+ case SIM_SH_FR0_REGNUM: case SIM_SH_FR1_REGNUM: case SIM_SH_FR2_REGNUM:
+ case SIM_SH_FR3_REGNUM: case SIM_SH_FR4_REGNUM: case SIM_SH_FR5_REGNUM:
+ case SIM_SH_FR6_REGNUM: case SIM_SH_FR7_REGNUM: case SIM_SH_FR8_REGNUM:
+ case SIM_SH_FR9_REGNUM: case SIM_SH_FR10_REGNUM: case SIM_SH_FR11_REGNUM:
+ case SIM_SH_FR12_REGNUM: case SIM_SH_FR13_REGNUM: case SIM_SH_FR14_REGNUM:
+ case SIM_SH_FR15_REGNUM:
+ SET_FI (rn - SIM_SH_FR0_REGNUM, val);
+ break;
+ case SIM_SH_DSR_REGNUM:
+ DSR = val;
+ break;
+ case SIM_SH_A0G_REGNUM:
+ A0G = val;
+ break;
+ case SIM_SH_A0_REGNUM:
+ A0 = val;
+ break;
+ case SIM_SH_A1G_REGNUM:
+ A1G = val;
+ break;
+ case SIM_SH_A1_REGNUM:
+ A1 = val;
+ break;
+ case SIM_SH_M0_REGNUM:
+ M0 = val;
+ break;
+ case SIM_SH_M1_REGNUM:
+ M1 = val;
+ break;
+ case SIM_SH_X0_REGNUM:
+ X0 = val;
+ break;
+ case SIM_SH_X1_REGNUM:
+ X1 = val;
+ break;
+ case SIM_SH_Y0_REGNUM:
+ Y0 = val;
+ break;
+ case SIM_SH_Y1_REGNUM:
+ Y1 = val;
+ break;
+ case SIM_SH_MOD_REGNUM:
+ SET_MOD (val);
+ break;
+ case SIM_SH_RS_REGNUM:
+ RS = val;
+ break;
+ case SIM_SH_RE_REGNUM:
+ RE = val;
+ break;
+ case SIM_SH_SSR_REGNUM:
+ SSR = val;
+ break;
+ case SIM_SH_SPC_REGNUM:
+ SPC = val;
+ break;
+ /* The rn_bank idiosyncracies are not due to hardware differences, but to
+ a weird aliasing naming scheme for sh3 / sh3e / sh4. */
+ case SIM_SH_R0_BANK0_REGNUM: case SIM_SH_R1_BANK0_REGNUM:
+ case SIM_SH_R2_BANK0_REGNUM: case SIM_SH_R3_BANK0_REGNUM:
+ case SIM_SH_R4_BANK0_REGNUM: case SIM_SH_R5_BANK0_REGNUM:
+ case SIM_SH_R6_BANK0_REGNUM: case SIM_SH_R7_BANK0_REGNUM:
+ if (saved_state.asregs.bfd_mach == bfd_mach_sh2a)
+ {
+ rn -= SIM_SH_R0_BANK0_REGNUM;
+ saved_state.asregs.regstack[gdb_bank_number].regs[rn] = val;
+ }
+ else
+ if (SR_MD && SR_RB)
+ Rn_BANK (rn - SIM_SH_R0_BANK0_REGNUM) = val;
+ else
+ saved_state.asregs.regs[rn - SIM_SH_R0_BANK0_REGNUM] = val;
+ break;
+ case SIM_SH_R0_BANK1_REGNUM: case SIM_SH_R1_BANK1_REGNUM:
+ case SIM_SH_R2_BANK1_REGNUM: case SIM_SH_R3_BANK1_REGNUM:
+ case SIM_SH_R4_BANK1_REGNUM: case SIM_SH_R5_BANK1_REGNUM:
+ case SIM_SH_R6_BANK1_REGNUM: case SIM_SH_R7_BANK1_REGNUM:
+ if (saved_state.asregs.bfd_mach == bfd_mach_sh2a)
+ {
+ rn -= SIM_SH_R0_BANK1_REGNUM;
+ saved_state.asregs.regstack[gdb_bank_number].regs[rn + 8] = val;
+ }
+ else
+ if (SR_MD && SR_RB)
+ saved_state.asregs.regs[rn - SIM_SH_R0_BANK1_REGNUM] = val;
+ else
+ Rn_BANK (rn - SIM_SH_R0_BANK1_REGNUM) = val;
+ break;
+ case SIM_SH_R0_BANK_REGNUM: case SIM_SH_R1_BANK_REGNUM:
+ case SIM_SH_R2_BANK_REGNUM: case SIM_SH_R3_BANK_REGNUM:
+ case SIM_SH_R4_BANK_REGNUM: case SIM_SH_R5_BANK_REGNUM:
+ case SIM_SH_R6_BANK_REGNUM: case SIM_SH_R7_BANK_REGNUM:
+ SET_Rn_BANK (rn - SIM_SH_R0_BANK_REGNUM, val);
+ break;
+ case SIM_SH_TBR_REGNUM:
+ TBR = val;
+ break;
+ case SIM_SH_IBNR_REGNUM:
+ IBNR = val;
+ break;
+ case SIM_SH_IBCR_REGNUM:
+ IBCR = val;
+ break;
+ case SIM_SH_BANK_REGNUM:
+ /* This is a pseudo-register maintained just for gdb.
+ It tells us what register bank gdb would like to read/write. */
+ gdb_bank_number = val;
+ break;
+ case SIM_SH_BANK_MACL_REGNUM:
+ saved_state.asregs.regstack[gdb_bank_number].regs[REGBANK_MACL] = val;
+ break;
+ case SIM_SH_BANK_GBR_REGNUM:
+ saved_state.asregs.regstack[gdb_bank_number].regs[REGBANK_GBR] = val;
+ break;
+ case SIM_SH_BANK_PR_REGNUM:
+ saved_state.asregs.regstack[gdb_bank_number].regs[REGBANK_PR] = val;
+ break;
+ case SIM_SH_BANK_IVN_REGNUM:
+ saved_state.asregs.regstack[gdb_bank_number].regs[REGBANK_IVN] = val;
+ break;
+ case SIM_SH_BANK_MACH_REGNUM:
+ saved_state.asregs.regstack[gdb_bank_number].regs[REGBANK_MACH] = val;
+ break;
+ default:
+ return 0;
+ }
+ return length;
+}
+
+static int
+sh_reg_fetch (SIM_CPU *cpu, int rn, unsigned char *memory, int length)
+{
+ int val;
+
+ init_pointers ();
+ switch (rn)
+ {
+ case SIM_SH_R0_REGNUM: case SIM_SH_R1_REGNUM: case SIM_SH_R2_REGNUM:
+ case SIM_SH_R3_REGNUM: case SIM_SH_R4_REGNUM: case SIM_SH_R5_REGNUM:
+ case SIM_SH_R6_REGNUM: case SIM_SH_R7_REGNUM: case SIM_SH_R8_REGNUM:
+ case SIM_SH_R9_REGNUM: case SIM_SH_R10_REGNUM: case SIM_SH_R11_REGNUM:
+ case SIM_SH_R12_REGNUM: case SIM_SH_R13_REGNUM: case SIM_SH_R14_REGNUM:
+ case SIM_SH_R15_REGNUM:
+ val = saved_state.asregs.regs[rn];
+ break;
+ case SIM_SH_PC_REGNUM:
+ val = saved_state.asregs.pc;
+ break;
+ case SIM_SH_PR_REGNUM:
+ val = PR;
+ break;
+ case SIM_SH_GBR_REGNUM:
+ val = GBR;
+ break;
+ case SIM_SH_VBR_REGNUM:
+ val = VBR;
+ break;
+ case SIM_SH_MACH_REGNUM:
+ val = MACH;
+ break;
+ case SIM_SH_MACL_REGNUM:
+ val = MACL;
+ break;
+ case SIM_SH_SR_REGNUM:
+ val = GET_SR ();
+ break;
+ case SIM_SH_FPUL_REGNUM:
+ val = FPUL;
+ break;
+ case SIM_SH_FPSCR_REGNUM:
+ val = GET_FPSCR ();
+ break;
+ case SIM_SH_FR0_REGNUM: case SIM_SH_FR1_REGNUM: case SIM_SH_FR2_REGNUM:
+ case SIM_SH_FR3_REGNUM: case SIM_SH_FR4_REGNUM: case SIM_SH_FR5_REGNUM:
+ case SIM_SH_FR6_REGNUM: case SIM_SH_FR7_REGNUM: case SIM_SH_FR8_REGNUM:
+ case SIM_SH_FR9_REGNUM: case SIM_SH_FR10_REGNUM: case SIM_SH_FR11_REGNUM:
+ case SIM_SH_FR12_REGNUM: case SIM_SH_FR13_REGNUM: case SIM_SH_FR14_REGNUM:
+ case SIM_SH_FR15_REGNUM:
+ val = FI (rn - SIM_SH_FR0_REGNUM);
+ break;
+ case SIM_SH_DSR_REGNUM:
+ val = DSR;
+ break;
+ case SIM_SH_A0G_REGNUM:
+ val = SEXT (A0G);
+ break;
+ case SIM_SH_A0_REGNUM:
+ val = A0;
+ break;
+ case SIM_SH_A1G_REGNUM:
+ val = SEXT (A1G);
+ break;
+ case SIM_SH_A1_REGNUM:
+ val = A1;
+ break;
+ case SIM_SH_M0_REGNUM:
+ val = M0;
+ break;
+ case SIM_SH_M1_REGNUM:
+ val = M1;
+ break;
+ case SIM_SH_X0_REGNUM:
+ val = X0;
+ break;
+ case SIM_SH_X1_REGNUM:
+ val = X1;
+ break;
+ case SIM_SH_Y0_REGNUM:
+ val = Y0;
+ break;
+ case SIM_SH_Y1_REGNUM:
+ val = Y1;
+ break;
+ case SIM_SH_MOD_REGNUM:
+ val = MOD;
+ break;
+ case SIM_SH_RS_REGNUM:
+ val = RS;
+ break;
+ case SIM_SH_RE_REGNUM:
+ val = RE;
+ break;
+ case SIM_SH_SSR_REGNUM:
+ val = SSR;
+ break;
+ case SIM_SH_SPC_REGNUM:
+ val = SPC;
+ break;
+ /* The rn_bank idiosyncracies are not due to hardware differences, but to
+ a weird aliasing naming scheme for sh3 / sh3e / sh4. */
+ case SIM_SH_R0_BANK0_REGNUM: case SIM_SH_R1_BANK0_REGNUM:
+ case SIM_SH_R2_BANK0_REGNUM: case SIM_SH_R3_BANK0_REGNUM:
+ case SIM_SH_R4_BANK0_REGNUM: case SIM_SH_R5_BANK0_REGNUM:
+ case SIM_SH_R6_BANK0_REGNUM: case SIM_SH_R7_BANK0_REGNUM:
+ if (saved_state.asregs.bfd_mach == bfd_mach_sh2a)
+ {
+ rn -= SIM_SH_R0_BANK0_REGNUM;
+ val = saved_state.asregs.regstack[gdb_bank_number].regs[rn];
+ }
+ else
+ val = (SR_MD && SR_RB
+ ? Rn_BANK (rn - SIM_SH_R0_BANK0_REGNUM)
+ : saved_state.asregs.regs[rn - SIM_SH_R0_BANK0_REGNUM]);
+ break;
+ case SIM_SH_R0_BANK1_REGNUM: case SIM_SH_R1_BANK1_REGNUM:
+ case SIM_SH_R2_BANK1_REGNUM: case SIM_SH_R3_BANK1_REGNUM:
+ case SIM_SH_R4_BANK1_REGNUM: case SIM_SH_R5_BANK1_REGNUM:
+ case SIM_SH_R6_BANK1_REGNUM: case SIM_SH_R7_BANK1_REGNUM:
+ if (saved_state.asregs.bfd_mach == bfd_mach_sh2a)
+ {
+ rn -= SIM_SH_R0_BANK1_REGNUM;
+ val = saved_state.asregs.regstack[gdb_bank_number].regs[rn + 8];
+ }
+ else
+ val = (! SR_MD || ! SR_RB
+ ? Rn_BANK (rn - SIM_SH_R0_BANK1_REGNUM)
+ : saved_state.asregs.regs[rn - SIM_SH_R0_BANK1_REGNUM]);
+ break;
+ case SIM_SH_R0_BANK_REGNUM: case SIM_SH_R1_BANK_REGNUM:
+ case SIM_SH_R2_BANK_REGNUM: case SIM_SH_R3_BANK_REGNUM:
+ case SIM_SH_R4_BANK_REGNUM: case SIM_SH_R5_BANK_REGNUM:
+ case SIM_SH_R6_BANK_REGNUM: case SIM_SH_R7_BANK_REGNUM:
+ val = Rn_BANK (rn - SIM_SH_R0_BANK_REGNUM);
+ break;
+ case SIM_SH_TBR_REGNUM:
+ val = TBR;
+ break;
+ case SIM_SH_IBNR_REGNUM:
+ val = IBNR;
+ break;
+ case SIM_SH_IBCR_REGNUM:
+ val = IBCR;
+ break;
+ case SIM_SH_BANK_REGNUM:
+ /* This is a pseudo-register maintained just for gdb.
+ It tells us what register bank gdb would like to read/write. */
+ val = gdb_bank_number;
+ break;
+ case SIM_SH_BANK_MACL_REGNUM:
+ val = saved_state.asregs.regstack[gdb_bank_number].regs[REGBANK_MACL];
+ break;
+ case SIM_SH_BANK_GBR_REGNUM:
+ val = saved_state.asregs.regstack[gdb_bank_number].regs[REGBANK_GBR];
+ break;
+ case SIM_SH_BANK_PR_REGNUM:
+ val = saved_state.asregs.regstack[gdb_bank_number].regs[REGBANK_PR];
+ break;
+ case SIM_SH_BANK_IVN_REGNUM:
+ val = saved_state.asregs.regstack[gdb_bank_number].regs[REGBANK_IVN];
+ break;
+ case SIM_SH_BANK_MACH_REGNUM:
+ val = saved_state.asregs.regstack[gdb_bank_number].regs[REGBANK_MACH];
+ break;
+ default:
+ return 0;
+ }
+ * (int *) memory = swap (val);
+ return length;
+}
+
+void
+sim_stop_reason (SIM_DESC sd, enum sim_stop *reason, int *sigrc)
+{
+ /* The SH simulator uses SIGQUIT to indicate that the program has
+ exited, so we must check for it here and translate it to exit. */
+ if (saved_state.asregs.exception == SIGQUIT)
+ {
+ *reason = sim_exited;
+ *sigrc = saved_state.asregs.regs[5];
+ }
+ else
+ {
+ *reason = sim_stopped;
+ *sigrc = saved_state.asregs.exception;
+ }
+}
+
+void
+sim_info (SIM_DESC sd, int verbose)
+{
+ double timetaken =
+ (double) saved_state.asregs.ticks / (double) now_persec ();
+ double virttime = saved_state.asregs.cycles / 36.0e6;
+
+ sim_io_printf (sd, "\n\n# instructions executed %10d\n",
+ saved_state.asregs.insts);
+ sim_io_printf (sd, "# cycles %10d\n",
+ saved_state.asregs.cycles);
+ sim_io_printf (sd, "# pipeline stalls %10d\n",
+ saved_state.asregs.stalls);
+ sim_io_printf (sd, "# misaligned load/store %10d\n",
+ saved_state.asregs.memstalls);
+ sim_io_printf (sd, "# real time taken %10.4f\n", timetaken);
+ sim_io_printf (sd, "# virtual time taken %10.4f\n", virttime);
+ sim_io_printf (sd, "# profiling size %10d\n", sim_profile_size);
+ sim_io_printf (sd, "# profiling frequency %10d\n",
+ saved_state.asregs.profile);
+ sim_io_printf (sd, "# profile maxpc %10x\n",
+ (1 << sim_profile_size) << PROFILE_SHIFT);
+
+ if (timetaken != 0)
+ {
+ sim_io_printf (sd, "# cycles/second %10d\n",
+ (int) (saved_state.asregs.cycles / timetaken));
+ sim_io_printf (sd, "# simulation ratio %10.4f\n",
+ virttime / timetaken);
+ }
+}
+
+static sim_cia
+sh_pc_get (sim_cpu *cpu)
+{
+ return saved_state.asregs.pc;
+}
+
+static void
+sh_pc_set (sim_cpu *cpu, sim_cia pc)
+{
+ saved_state.asregs.pc = pc;
+}
+
+static void
+free_state (SIM_DESC sd)
+{
+ if (STATE_MODULES (sd) != NULL)
+ sim_module_uninstall (sd);
+ sim_cpu_free_all (sd);
+ sim_state_free (sd);
+}
+
+SIM_DESC
+sim_open (SIM_OPEN_KIND kind, host_callback *cb,
+ struct bfd *abfd, char * const *argv)
+{
+ char **p;
+ int i;
+ union
+ {
+ int i;
+ short s[2];
+ char c[4];
+ }
+ mem_word;
+
+ SIM_DESC sd = sim_state_alloc (kind, cb);
+ SIM_ASSERT (STATE_MAGIC (sd) == SIM_MAGIC_NUMBER);
+
+ /* The cpu data is kept in a separately allocated chunk of memory. */
+ if (sim_cpu_alloc_all (sd, 1, /*cgen_cpu_max_extra_bytes ()*/0) != SIM_RC_OK)
+ {
+ free_state (sd);
+ return 0;
+ }
+
+ if (sim_pre_argv_init (sd, argv[0]) != SIM_RC_OK)
+ {
+ free_state (sd);
+ return 0;
+ }
+
+ /* The parser will print an error message for us, so we silently return. */
+ if (sim_parse_args (sd, argv) != SIM_RC_OK)
+ {
+ free_state (sd);
+ return 0;
+ }
+
+ /* Check for/establish the a reference program image. */
+ if (sim_analyze_program (sd,
+ (STATE_PROG_ARGV (sd) != NULL
+ ? *STATE_PROG_ARGV (sd)
+ : NULL), abfd) != SIM_RC_OK)
+ {
+ free_state (sd);
+ return 0;
+ }
+
+ /* Configure/verify the target byte order and other runtime
+ configuration options. */
+ if (sim_config (sd) != SIM_RC_OK)
+ {
+ sim_module_uninstall (sd);
+ return 0;
+ }
+
+ if (sim_post_argv_init (sd) != SIM_RC_OK)
+ {
+ /* Uninstall the modules to avoid memory leaks,
+ file descriptor leaks, etc. */
+ sim_module_uninstall (sd);
+ return 0;
+ }
+
+ /* CPU specific initialization. */
+ for (i = 0; i < MAX_NR_PROCESSORS; ++i)
+ {
+ SIM_CPU *cpu = STATE_CPU (sd, i);
+
+ CPU_REG_FETCH (cpu) = sh_reg_fetch;
+ CPU_REG_STORE (cpu) = sh_reg_store;
+ CPU_PC_FETCH (cpu) = sh_pc_get;
+ CPU_PC_STORE (cpu) = sh_pc_set;
+ }
+
+ for (p = argv + 1; *p != NULL; ++p)
+ {
+ if (isdigit (**p))
+ parse_and_set_memory_size (sd, *p);
+ }
+
+ if (abfd)
+ init_dsp (abfd);
+
+ for (i = 4; (i -= 2) >= 0; )
+ mem_word.s[i >> 1] = i;
+ global_endianw = mem_word.i >> (target_little_endian ? 0 : 16) & 0xffff;
+
+ for (i = 4; --i >= 0; )
+ mem_word.c[i] = i;
+ endianb = mem_word.i >> (target_little_endian ? 0 : 24) & 0xff;
+
+ return sd;
+}
+
+static void
+parse_and_set_memory_size (SIM_DESC sd, const char *str)
+{
+ int n;
+
+ n = strtol (str, NULL, 10);
+ if (n > 0 && n <= 31)
+ sim_memory_size = n;
+ else
+ sim_io_printf (sd, "Bad memory size %d; must be 1 to 31, inclusive\n", n);
+}
+
+SIM_RC
+sim_create_inferior (SIM_DESC sd, struct bfd *prog_bfd,
+ char * const *argv, char * const *env)
+{
+ /* Clear the registers. */
+ memset (&saved_state, 0,
+ (char*) &saved_state.asregs.end_of_registers - (char*) &saved_state);
+
+ /* Set the PC. */
+ if (prog_bfd != NULL)
+ saved_state.asregs.pc = bfd_get_start_address (prog_bfd);
+
+ /* Set the bfd machine type. */
+ if (prog_bfd != NULL)
+ saved_state.asregs.bfd_mach = bfd_get_mach (prog_bfd);
+
+ if (prog_bfd != NULL)
+ init_dsp (prog_bfd);
+
+ return SIM_RC_OK;
+}
+
+void
+sim_do_command (SIM_DESC sd, const char *cmd)
+{
+ const char *sms_cmd = "set-memory-size";
+ int cmdsize;
+
+ if (cmd == NULL || *cmd == '\0')
+ {
+ cmd = "help";
+ }
+
+ cmdsize = strlen (sms_cmd);
+ if (strncmp (cmd, sms_cmd, cmdsize) == 0
+ && strchr (" \t", cmd[cmdsize]) != NULL)
+ {
+ parse_and_set_memory_size (sd, cmd + cmdsize + 1);
+ }
+ else if (strcmp (cmd, "help") == 0)
+ {
+ sim_io_printf (sd, "List of SH simulator commands:\n\n");
+ sim_io_printf (sd, "set-memory-size <n> -- Set the number of address bits to use\n");
+ sim_io_printf (sd, "\n");
+ }
+ else
+ {
+ sim_io_printf (sd, "Error: \"%s\" is not a valid SH simulator command.\n", cmd);