+ * configure: Regenerated to track ../common/aclocal.m4 changes.
+
+1999-08-30 Doug Evans <devans@casey.cygnus.com>
+
+ * sim/arm/thumb/allthumb.exp: New driver for thumb testcases.
+ * sim/arm/allinsn.exp: New driver for arm testcases.
+
+ * lib/sim-defs.exp (run_sim_test): Rename all_machs arg to
+ requested_machs, now is list of machs to run tests for.
+ Delete locals AS,ASFLAGS,LD,LDFLAGS. Use target_assemble
+ and target_link instead.
+
+1999-07-16 Ben Elliston <bje@cygnus.com>
+
+ * sim/arm/misaligned1.ms: New test case.
+ * sim/arm/misaligned2.ms: Likewise.
+ * sim/arm/misaligned3.ms: Likewise.
+
+1999-07-16 Ben Elliston <bje@cygnus.com>
+
+ * sim/arm/misc.exp: Enable basic tests.
+
+1999-04-21 Doug Evans <devans@casey.cygnus.com>
+
+ * sim/m32r/nop.cgs: Add missing nop insn.
+
+Mon Mar 22 13:28:56 1999 Dave Brolley <brolley@cygnus.com>
+
+ * sim/fr30/stb.cgs: Correct for unaligned access.
+ * sim/fr30/sth.cgs: Correct for unaligned access.
+ * sim/fr30/ldub.cgs: Fix typo: lduh->ldub. Correct
+ for unaligned access.
+ * sim/fr30/and.cgs: Test unaligned access.
+
+Fri Feb 5 12:41:11 1999 Doug Evans <devans@canuck.cygnus.com>
+
+ * lib/sim-defs.exp (sim_run): Print simulator arguments log message.
+
+1999-01-05 Doug Evans <devans@casey.cygnus.com>
+
+ * lib/sim-defs.exp (run_sim_test): New arg all_machs.
+ * sim/fr30/allinsn.exp: Update.
+ * sim/fr30/misc.exp: Update.
+ * sim/m32r/allinsn.exp: Update.
+ * sim/m32r/misc.exp: Update.
+
+Fri Dec 18 17:19:34 1998 Dave Brolley <brolley@cygnus.com>
+
+ * sim/fr30/ldres.cgs: New testcase.
+ * sim/fr30/copld.cgs: New testcase.
+ * sim/fr30/copst.cgs: New testcase.
+ * sim/fr30/copsv.cgs: New testcase.
+ * sim/fr30/nop.cgs: New testcase.
+ * sim/fr30/andccr.cgs: New testcase.
+ * sim/fr30/orccr.cgs: New testcase.
+ * sim/fr30/addsp.cgs: New testcase.
+ * sim/fr30/stilm.cgs: New testcase.
+ * sim/fr30/extsb.cgs: New testcase.
+ * sim/fr30/extub.cgs: New testcase.
+ * sim/fr30/extsh.cgs: New testcase.
+ * sim/fr30/extuh.cgs: New testcase.
+ * sim/fr30/enter.cgs: New testcase.
+ * sim/fr30/leave.cgs: New testcase.
+ * sim/fr30/xchb.cgs: New testcase.
+ * sim/fr30/dmovb.cgs: New testcase.
+ * sim/fr30/dmov.cgs: New testcase.
+ * sim/fr30/dmovh.cgs: New testcase.
+
+Thu Dec 17 17:18:43 1998 Dave Brolley <brolley@cygnus.com>
+
+ * sim/fr30/testutils.inc (take_branch{_d},no_branch{_d}): New macros.
+ * sim/fr30/ret.cgs: Add tests fir ret:d.
+ * sim/fr30/inte.cgs: New testcase.
+ * sim/fr30/reti.cgs: New testcase.
+ * sim/fr30/bra.cgs: New testcase.
+ * sim/fr30/bno.cgs: New testcase.
+ * sim/fr30/beq.cgs: New testcase.
+ * sim/fr30/bne.cgs: New testcase.
+ * sim/fr30/bc.cgs: New testcase.
+ * sim/fr30/bnc.cgs: New testcase.
+ * sim/fr30/bn.cgs: New testcase.
+ * sim/fr30/bp.cgs: New testcase.
+ * sim/fr30/bv.cgs: New testcase.
+ * sim/fr30/bnv.cgs: New testcase.
+ * sim/fr30/blt.cgs: New testcase.
+ * sim/fr30/bge.cgs: New testcase.
+ * sim/fr30/ble.cgs: New testcase.
+ * sim/fr30/bgt.cgs: New testcase.
+ * sim/fr30/bls.cgs: New testcase.
+ * sim/fr30/bhi.cgs: New testcase.
+
+Tue Dec 15 17:47:13 1998 Dave Brolley <brolley@cygnus.com>
+
+ * sim/fr30/div.cgs (int): Add signed division scenario.
+ * sim/fr30/int.cgs (int): Complete testcase.
+ * sim/fr30/testutils.inc (_start): Initialize tbr.
+ (test_s_user,test_s_system,set_i,test_i): New macros.
+
+1998-12-14 Doug Evans <devans@casey.cygnus.com>
+
+ * lib/sim-defs.exp (run_sim_test): New option xerror, for expected
+ errors. Translate \n sequences in expected output to newline char.
+ (slurp_options): Make parentheses optional.
+ (sim_run): Look for board_info sim,options.
+ * sim/fr30/hello.ms: Add trailing \n to expected output.
+ * sim/m32r/hello.ms: Ditto.
+ * sim/m32r/hw-trap.ms: Ditto.
+
+ * sim/m32r/trap.cgs: Properly align trap2_handler.
+
+ * sim/m32r/uread16.ms: New testcase.
+ * sim/m32r/uread32.ms: New testcase.
+ * sim/m32r/uwrite16.ms: New testcase.
+ * sim/m32r/uwrite32.ms: New testcase.
+
+1998-12-14 Dave Brolley <brolley@cygnus.com>
+
+ * sim/fr30/call.cgs: Test ret here as well.
+ * sim/fr30/ld.cgs: Remove bogus comment.
+ * sim/fr30/testutils.inc (save_rp,restore_rp): New macros.
+ * sim/fr30/div.ms: New testcase.
+ * sim/fr30/st.cgs: New testcase.
+ * sim/fr30/sth.cgs: New testcase.
+ * sim/fr30/stb.cgs: New testcase.
+ * sim/fr30/mov.cgs: New testcase.
+ * sim/fr30/jmp.cgs: New testcase.
+ * sim/fr30/ret.cgs: New testcase.
+ * sim/fr30/int.cgs: New testcase.
+
+Thu Dec 10 18:46:25 1998 Dave Brolley <brolley@cygnus.com>
+
+ * sim/fr30/div0s.cgs: New testcase.
+ * sim/fr30/div0u.cgs: New testcase.
+ * sim/fr30/div1.cgs: New testcase.
+ * sim/fr30/div2.cgs: New testcase.
+ * sim/fr30/div3.cgs: New testcase.
+ * sim/fr30/div4s.cgs: New testcase.
+ * sim/fr30/testutils.inc (mvi_h_dr,set_dbits,test_dbits): New Macros.
+
+Tue Dec 8 13:16:53 1998 Dave Brolley <brolley@cygnus.com>
+
+ * sim/fr30/testutils.inc (set_s_user): Correct Mask.
+ (set_s_system): Correct Mask.
+ * sim/fr30/ld.cgs (ld): Move previously failing test back
+ into place.
+ * sim/fr30/ldm0.cgs: New testcase.
+ * sim/fr30/ldm1.cgs: New testcase.
+ * sim/fr30/stm0.cgs: New testcase.
+ * sim/fr30/stm1.cgs: New testcase.
+
+Thu Dec 3 14:20:03 1998 Dave Brolley <brolley@cygnus.com>
+
+ * sim/fr30/ld.cgs: Implement more loads.
+ * sim/fr30/call.cgs: New testcase.
+ * sim/fr30/testutils.inc (testr_h_dr): New macro.
+ (set_s_user,set_s_system): New macros.
+
+ * sim/fr30: New Directory.
+
+Wed Nov 18 10:50:19 1998 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * common/bits-gen.c (main): Add BYTE_ORDER so that it matches
+ recent sim/common/sim-basics.h changes.
+ * common/Makefile.in: Update.
+
+Fri Oct 30 00:37:31 1998 Felix Lee <flee@cygnus.com>