+// CVTF.DW
+rrrr,011111100100 + wwwww,10001010000:F_I:::cvtf_dw
+*v850e2v3
+*v850e3v5
+"cvtf.dw r<reg2e>, r<reg3>"
+{
+ int32 ans;
+ sim_fpu wop;
+ sim_fpu_status status;
+
+ sim_fpu_232to (&wop, GR[reg2e+1], GR[reg2e]);
+ TRACE_FP_INPUT_FPU1 (&wop);
+
+ status = sim_fpu_round_32 (&wop, FPSR_GET_ROUND(), sim_fpu_denorm_zero);
+ status |= sim_fpu_to32i (&ans, &wop, FPSR_GET_ROUND());
+
+ check_cvt_fi(sd, status, 1);
+
+ GR[reg3] = ans;
+ TRACE_FP_RESULT_WORD1 (ans);
+}
+
+// CVTF.LD
+rrrr,011111100001 + wwww,010001010010:F_I:::cvtf_ld
+*v850e2v3
+*v850e3v5
+"cvtf.ld r<reg2e>, r<reg3e>"
+{
+ signed64 op;
+ sim_fpu wop;
+ sim_fpu_status status;
+
+ op = ((signed64)GR[reg2e+1] << 32L) | GR[reg2e];
+ TRACE_FP_INPUT_WORD2 (GR[reg2e], GR[reg2e+1]);
+
+ sim_fpu_i64to (&wop, op, FPSR_GET_ROUND());
+ status = sim_fpu_round_64 (&wop, FPSR_GET_ROUND(), sim_fpu_denorm_zero);
+
+ check_cvt_if(sd, status, 1);
+
+ sim_fpu_to232 (&GR[reg3e+1], &GR[reg3e], &wop);
+ TRACE_FP_RESULT_FPU1 (&wop);
+}
+
+// CVTF.LS
+rrrr,011111100001 + wwwww,10001000010:F_I:::cvtf_ls
+*v850e2v3
+*v850e3v5
+"cvtf.ls r<reg2e>, r<reg3>"
+{
+ signed64 op;
+ sim_fpu wop;
+ sim_fpu_status status;
+
+ op = ((signed64)GR[reg2e+1] << 32L) | GR[reg2e];
+ TRACE_FP_INPUT_WORD2 (GR[reg2e], GR[reg2e+1]);
+
+ sim_fpu_i64to (&wop, op, FPSR_GET_ROUND());
+ status = sim_fpu_round_32 (&wop, FPSR_GET_ROUND(), sim_fpu_denorm_zero);
+
+ check_cvt_if(sd, status, 0);
+
+ sim_fpu_to32 (&GR[reg3], &wop);
+ TRACE_FP_RESULT_FPU1 (&wop);
+}
+
+// CVTF.SD
+rrrrr,11111100010 + wwww,010001010010:F_I:::cvtf_sd
+*v850e2v3
+*v850e3v5
+"cvtf.sd r<reg2>, r<reg3e>"
+{
+ sim_fpu wop;
+ sim_fpu_status status;
+
+ sim_fpu_32to (&wop, GR[reg2]);
+ TRACE_FP_INPUT_FPU1 (&wop);
+ status = sim_fpu_round_64 (&wop, FPSR_GET_ROUND(), sim_fpu_denorm_underflow_inexact);
+
+ check_cvt_ff(sd, status, 1);
+
+ sim_fpu_to232 (&GR[reg3e+1], &GR[reg3e], &wop);
+ TRACE_FP_RESULT_FPU1 (&wop);
+}
+
+// CVTF.SL
+rrrrr,11111100100 + wwww,010001000100:F_I:::cvtf_sl
+*v850e2v3
+*v850e3v5
+"cvtf.sl r<reg2>, r<reg3e>"
+{
+ signed64 ans;
+ sim_fpu wop;
+ sim_fpu_status status;
+
+ sim_fpu_32to (&wop, GR[reg2]);
+ TRACE_FP_INPUT_FPU1 (&wop);
+
+ status = sim_fpu_round_64 (&wop, FPSR_GET_ROUND(), sim_fpu_denorm_zero);
+ status |= sim_fpu_to64i (&ans, &wop, FPSR_GET_ROUND());
+
+ check_cvt_fi(sd, status, 0);
+
+ GR[reg3e] = ans;
+ GR[reg3e+1] = ans >> 32L;
+ TRACE_FP_RESULT_WORD2 (GR[reg3e], GR[reg3e+1]);
+}
+
+// CVTF.SW
+rrrrr,11111100100 + wwwww,10001000000:F_I:::cvtf_sw
+*v850e2v3
+*v850e3v5
+"cvtf.sw r<reg2>, r<reg3>"
+{
+ int32 ans;
+ sim_fpu wop;
+ sim_fpu_status status;
+
+ sim_fpu_32to (&wop, GR[reg2]);
+ TRACE_FP_INPUT_FPU1 (&wop);
+
+ status = sim_fpu_round_32 (&wop, FPSR_GET_ROUND(), sim_fpu_denorm_zero);
+ status |= sim_fpu_to32i (&ans, &wop, sim_fpu_round_zero);
+
+ check_cvt_fi(sd, status, 0);
+
+ GR[reg3] = ans;
+ TRACE_FP_RESULT_WORD1 (ans);
+}
+
+// CVTF.WD
+rrrrr,11111100000 + wwww,010001010010:F_I:::cvtf_wd
+*v850e2v3
+*v850e3v5
+"cvtf.wd r<reg2>, r<reg3e>"
+{
+ sim_fpu wop;
+ sim_fpu_status status;
+
+ TRACE_FP_INPUT_WORD1 (GR[reg2]);
+ sim_fpu_i32to (&wop, GR[reg2], FPSR_GET_ROUND());
+ status = sim_fpu_round_64 (&wop, FPSR_GET_ROUND(), sim_fpu_denorm_zero);
+
+ check_cvt_if(sd, status, 1);
+
+ sim_fpu_to232 (&GR[reg3e+1], &GR[reg3e], &wop);
+ TRACE_FP_RESULT_FPU1 (&wop);
+}
+
+// CVTF.WS
+rrrrr,11111100000 + wwwww,10001000010:F_I:::cvtf_ws
+*v850e2v3
+*v850e3v5
+"cvtf.ws r<reg2>, r<reg3>"
+{
+ sim_fpu wop;
+ sim_fpu_status status;
+
+ TRACE_FP_INPUT_WORD1 (GR[reg2]);
+ sim_fpu_i32to (&wop, GR[reg2], FPSR_GET_ROUND());
+ status = sim_fpu_round_32 (&wop, FPSR_GET_ROUND(), sim_fpu_denorm_zero);
+
+ check_cvt_if(sd, status, 0);
+
+ sim_fpu_to32 (&GR[reg3], &wop);
+ TRACE_FP_RESULT_FPU1 (&wop);
+}
+
+// DIVF.D
+rrrr,0111111,RRRR,0 + wwww,010001111110:F_I:::divf_d
+*v850e2v3
+*v850e3v5
+"divf.d r<reg1e>, r<reg2e>, r<reg3e>"
+{
+ sim_fpu ans, wop1, wop2;
+ sim_fpu_status status;
+
+ sim_fpu_232to (&wop1, GR[reg1e+1], GR[reg1e]);
+ sim_fpu_232to (&wop2, GR[reg2e+1], GR[reg2e]);
+ TRACE_FP_INPUT_FPU2 (&wop1, &wop2);
+
+ status = sim_fpu_div (&ans, &wop2, &wop1);
+ status |= sim_fpu_round_64 (&ans, FPSR_GET_ROUND(), sim_fpu_denorm_underflow_inexact);
+
+ update_fpsr (sd, status, FPSR_XEV | FPSR_XEZ | FPSR_XEI | FPSR_XEO | FPSR_XEU, 1);
+
+ sim_fpu_to232 (&GR[reg3e+1], &GR[reg3e], &ans);
+ TRACE_FP_RESULT_FPU1 (&ans);
+}
+
+// DIVF.S
+rrrrr,111111,RRRRR + wwwww,10001101110:F_I:::divf_s
+*v850e2v3
+*v850e3v5
+"divf.s r<reg1>, r<reg2>, r<reg3>"
+{
+ sim_fpu ans, wop1, wop2;
+ sim_fpu_status status;
+
+ sim_fpu_32to (&wop1, GR[reg1]);
+ sim_fpu_32to (&wop2, GR[reg2]);
+ TRACE_FP_INPUT_FPU2 (&wop1, &wop2);
+
+ status = sim_fpu_div (&ans, &wop2, &wop1);
+ status |= sim_fpu_round_32 (&ans, FPSR_GET_ROUND(), sim_fpu_denorm_underflow_inexact);
+
+ update_fpsr (sd, status, FPSR_XEV | FPSR_XEZ | FPSR_XEI | FPSR_XEO | FPSR_XEU, 0);
+
+ sim_fpu_to32 (&GR[reg3], &ans);
+ TRACE_FP_RESULT_FPU1 (&ans);
+}
+
+// MADDF.S
+rrrrr,111111,RRRRR + wwwww,101,W,00,WWWW,0:F_I:::maddf_s
+*v850e2v3
+"maddf.s r<reg1>, r<reg2>, r<reg3>, r<reg4>"
+{
+ sim_fpu ans, wop1, wop2, wop3;
+ sim_fpu_status status;
+
+ sim_fpu_32to (&wop1, GR[reg1]);
+ sim_fpu_32to (&wop2, GR[reg2]);
+ sim_fpu_32to (&wop3, GR[reg3]);
+ TRACE_FP_INPUT_FPU3 (&wop1, &wop2, &wop3);
+
+ status = sim_fpu_mul (&ans, &wop1, &wop2);
+ wop1 = ans;
+ status |= sim_fpu_add (&ans, &wop1, &wop3);
+ status |= sim_fpu_round_64 (&ans, FPSR_GET_ROUND(), sim_fpu_denorm_underflow_inexact);
+
+ update_fpsr (sd, status, FPSR_XEV | FPSR_XEI | FPSR_XEO | FPSR_XEU, 0);
+
+ sim_fpu_to32 (&GR[reg4], &ans);
+ TRACE_FP_RESULT_FPU1 (&ans);
+}
+
+// FMAF.S
+rrrrr,111111,RRRRR + wwwww,10011100000:F_I:::fmaf_s
+*v850e3v5
+"fmaf.s r<reg1>, r<reg2>, r<reg3>"
+{
+ sim_fpu ans, wop1, wop2, wop3;
+ sim_fpu_status status;
+
+ sim_fpu_32to (&wop1, GR[reg1]);
+ sim_fpu_32to (&wop2, GR[reg2]);
+ sim_fpu_32to (&wop3, GR[reg3]);
+ TRACE_FP_INPUT_FPU3 (&wop1, &wop2, &wop3);
+
+ status = sim_fpu_mul (&ans, &wop1, &wop2);
+ wop1 = ans;
+ status |= sim_fpu_add (&ans, &wop1, &wop3);
+ status |= sim_fpu_round_64 (&ans, FPSR_GET_ROUND(), sim_fpu_denorm_underflow_inexact);
+
+ update_fpsr (sd, status, FPSR_XEV | FPSR_XEI | FPSR_XEO | FPSR_XEU, 0);
+
+ sim_fpu_to32 (&GR[reg3], &ans);
+ TRACE_FP_RESULT_FPU1 (&ans);
+}
+
+// MAXF.D
+rrrr,0111111,RRRR,0 + wwww,010001111000:F_I:::maxf_d
+*v850e2v3
+*v850e3v5
+"maxf.d r<reg1e>, r<reg2e>, r<reg3e>"
+{
+ sim_fpu ans, wop1, wop2;
+
+ sim_fpu_232to (&wop1, GR[reg1e+1], GR[reg1e]);
+ sim_fpu_232to (&wop2, GR[reg2e+1], GR[reg2e]);
+ TRACE_FP_INPUT_FPU2 (&wop1, &wop2);
+
+ if (sim_fpu_is_nan(&wop1) || sim_fpu_is_nan(&wop2))
+ {
+ if (FPSR & FPSR_XEV)
+ {
+ SignalExceptionFPE(sd, 1);
+ }
+ else
+ {
+ ans = sim_fpu_qnan;
+ }
+ }
+ else if (FPSR & FPSR_FS
+ && ((sim_fpu_is_zero (&wop1) || sim_fpu_is_denorm (&wop1))
+ && (sim_fpu_is_zero (&wop2) || sim_fpu_is_denorm (&wop2))))
+ {
+ ans = sim_fpu_zero;
+ }
+ else
+ {
+ sim_fpu_max (&ans, &wop1, &wop2);
+ }
+
+ sim_fpu_to232 (&GR[reg3e+1], &GR[reg3e], &ans);
+ TRACE_FP_RESULT_FPU1 (&ans);
+}
+
+// MAXF.S
+rrrrr,111111,RRRRR + wwwww,10001101000:F_I:::maxf_s
+*v850e2v3
+*v850e3v5
+"maxf.s r<reg1>, r<reg2>, r<reg3>"
+{
+ sim_fpu ans, wop1, wop2;
+
+ sim_fpu_32to (&wop1, GR[reg1]);
+ sim_fpu_32to (&wop2, GR[reg2]);
+ TRACE_FP_INPUT_FPU2 (&wop1, &wop2);
+
+ if (sim_fpu_is_nan(&wop1) || sim_fpu_is_nan(&wop2))
+ {
+ if (FPSR & FPSR_XEV)
+ {
+ SignalExceptionFPE(sd, 0);
+ }
+ else
+ {
+ ans = sim_fpu_qnan;
+ }
+ }
+ else if ((FPSR & FPSR_FS)
+ && ((sim_fpu_is_zero (&wop1) || sim_fpu_is_denorm (&wop1))
+ && (sim_fpu_is_zero (&wop2)|| sim_fpu_is_denorm (&wop2))))
+ {
+ ans = sim_fpu_zero;
+ }
+ else
+ {
+ sim_fpu_max (&ans, &wop1, &wop2);
+ }
+
+ sim_fpu_to32 (&GR[reg3], &ans);
+ TRACE_FP_RESULT_FPU1 (&ans);
+}
+
+// MINF.D
+rrrr,0111111,RRRR,0 + wwww,010001111010:F_I:::minf_d
+*v850e2v3
+*v850e3v5
+"minf.d r<reg1e>, r<reg2e>, r<reg3e>"
+{
+ sim_fpu ans, wop1, wop2;
+
+ sim_fpu_232to (&wop1, GR[reg1e+1], GR[reg1e]);
+ sim_fpu_232to (&wop2, GR[reg2e+1], GR[reg2e]);
+ TRACE_FP_INPUT_FPU2 (&wop1, &wop2);
+
+ if (sim_fpu_is_nan(&wop1) || sim_fpu_is_nan(&wop2))
+ {
+ if (FPSR & FPSR_XEV)
+ {
+ SignalExceptionFPE(sd, 1);
+ }
+ else
+ {
+ ans = sim_fpu_qnan;
+ }
+ }
+ else if (FPSR & FPSR_FS
+ && ((sim_fpu_is_zero (&wop1) || sim_fpu_is_denorm (&wop1))
+ && (sim_fpu_is_zero (&wop2) || sim_fpu_is_denorm (&wop2))))
+ {
+ ans = sim_fpu_zero;
+ }
+ else
+ {
+ sim_fpu_min (&ans, &wop1, &wop2);
+ }
+
+ sim_fpu_to232 (&GR[reg3e+1], &GR[reg3e], &ans);
+ TRACE_FP_RESULT_FPU1 (&ans);
+}
+
+// MINF.S
+rrrrr,111111,RRRRR + wwwww,10001101010:F_I:::minf_s
+*v850e2v3
+*v850e3v5
+"minf.s r<reg1>, r<reg2>, r<reg3>"
+{
+ sim_fpu ans, wop1, wop2;
+
+ sim_fpu_32to (&wop1, GR[reg1]);
+ sim_fpu_32to (&wop2, GR[reg2]);
+ TRACE_FP_INPUT_FPU2 (&wop1, &wop2);
+
+ if (sim_fpu_is_nan(&wop1) || sim_fpu_is_nan(&wop2))
+ {
+ if (FPSR & FPSR_XEV)
+ {
+ SignalExceptionFPE(sd, 0);
+ }
+ else
+ {
+ ans = sim_fpu_qnan;
+ }
+ }
+ else if (FPSR & FPSR_FS
+ && ((sim_fpu_is_zero (&wop1) || sim_fpu_is_denorm (&wop1))
+ && (sim_fpu_is_zero (&wop2) || sim_fpu_is_denorm (&wop2))))
+ {
+ ans = sim_fpu_zero;
+ }
+ else
+ {
+ sim_fpu_min (&ans, &wop1, &wop2);
+ }
+
+ sim_fpu_to32 (&GR[reg3], &ans);
+ TRACE_FP_RESULT_FPU1 (&ans);
+}
+
+// MSUBF.S
+rrrrr,111111,RRRRR + wwwww,101,W,01,WWWW,0:F_I:::msubf_s
+*v850e2v3
+"msubf.s r<reg1>, r<reg2>, r<reg3>, r<reg4>"
+{
+ sim_fpu ans, wop1, wop2, wop3;
+ sim_fpu_status status;
+
+ sim_fpu_32to (&wop1, GR[reg1]);
+ sim_fpu_32to (&wop2, GR[reg2]);
+ sim_fpu_32to (&wop3, GR[reg3]);
+ TRACE_FP_INPUT_FPU3 (&wop1, &wop2, &wop3);
+
+ status = sim_fpu_mul (&ans, &wop1, &wop2);
+ status |= sim_fpu_round_64 (&ans, FPSR_GET_ROUND(), sim_fpu_denorm_underflow_inexact);
+ wop1 = ans;
+ status |= sim_fpu_sub (&ans, &wop1, &wop3);
+ status |= sim_fpu_round_64 (&ans, FPSR_GET_ROUND(), sim_fpu_denorm_underflow_inexact);
+
+ update_fpsr (sd, status, FPSR_XEV | FPSR_XEI | FPSR_XEO | FPSR_XEU, 0);
+
+ sim_fpu_to32 (&GR[reg4], &ans);
+ TRACE_FP_RESULT_FPU1 (&ans);
+}
+
+// FMSF.S
+rrrrr,111111,RRRRR + wwwww,10011100010:F_I:::fmsf_s
+*v850e3v5
+"fmsf.s r<reg1>, r<reg2>, r<reg3>"
+{
+ sim_fpu ans, wop1, wop2, wop3;
+ sim_fpu_status status;
+
+ sim_fpu_32to (&wop1, GR[reg1]);
+ sim_fpu_32to (&wop2, GR[reg2]);
+ sim_fpu_32to (&wop3, GR[reg3]);
+ TRACE_FP_INPUT_FPU3 (&wop1, &wop2, &wop3);
+
+ status = sim_fpu_mul (&ans, &wop1, &wop2);
+ status |= sim_fpu_round_64 (&ans, FPSR_GET_ROUND(), sim_fpu_denorm_underflow_inexact);
+ wop1 = ans;
+ status |= sim_fpu_sub (&ans, &wop1, &wop3);
+ status |= sim_fpu_round_64 (&ans, FPSR_GET_ROUND(), sim_fpu_denorm_underflow_inexact);
+
+ update_fpsr (sd, status, FPSR_XEV | FPSR_XEI | FPSR_XEO | FPSR_XEU, 0);
+
+ sim_fpu_to32 (&GR[reg3], &ans);
+ TRACE_FP_RESULT_FPU1 (&ans);
+}
+
+// MULF.D
+rrrr,0111111,RRRR,0 + wwww,010001110100:F_I:::mulf_d
+*v850e2v3
+*v850e3v5
+"mulf.d r<reg1e>, r<reg2e>, r<reg3e>"
+{
+ sim_fpu ans, wop1, wop2;
+ sim_fpu_status status;
+
+ sim_fpu_232to (&wop1, GR[reg1e+1], GR[reg1e]);
+ sim_fpu_232to (&wop2, GR[reg2e+1], GR[reg2e]);
+ TRACE_FP_INPUT_FPU2 (&wop1, &wop2);
+
+ status = sim_fpu_mul (&ans, &wop1, &wop2);
+ status |= sim_fpu_round_64 (&ans, FPSR_GET_ROUND(), sim_fpu_denorm_underflow_inexact);
+
+ update_fpsr (sd, status, FPSR_XEV | FPSR_XEI | FPSR_XEO | FPSR_XEU, 1);
+
+ sim_fpu_to232 (&GR[reg3e+1], &GR[reg3e], &ans);
+ TRACE_FP_RESULT_FPU1 (&ans);
+}
+
+// MULF.S
+rrrrr,111111,RRRRR + wwwww,10001100100:F_I:::mulf_s
+*v850e2v3
+*v850e3v5
+"mulf.s r<reg1>, r<reg2>, r<reg3>"
+{
+ sim_fpu ans, wop1, wop2;
+ sim_fpu_status status;
+
+ sim_fpu_32to (&wop1, GR[reg1]);
+ sim_fpu_32to (&wop2, GR[reg2]);
+ TRACE_FP_INPUT_FPU2 (&wop1, &wop2);
+
+ status = sim_fpu_mul (&ans, &wop1, &wop2);
+ status |= sim_fpu_round_32 (&ans, FPSR_GET_ROUND(), sim_fpu_denorm_underflow_inexact);
+
+ update_fpsr (sd, status, FPSR_XEV | FPSR_XEI | FPSR_XEO | FPSR_XEU, 0);
+
+ sim_fpu_to32 (&GR[reg3], &ans);
+ TRACE_FP_RESULT_FPU1 (&ans);
+}
+
+// NEGF.D
+rrrr,011111100001 + wwww,010001011000:F_I:::negf_d
+*v850e2v3
+*v850e3v5
+"negf.d r<reg2e>, r<reg3e>"
+{
+ sim_fpu ans, wop;
+ sim_fpu_status status;
+
+ sim_fpu_232to (&wop, GR[reg2e+1], GR[reg2e]);
+ TRACE_FP_INPUT_FPU1 (&wop);
+
+ status = sim_fpu_neg (&ans, &wop);
+
+ check_invalid_snan(sd, status, 1);
+
+ sim_fpu_to232 (&GR[reg3e+1], &GR[reg3e], &ans);
+ TRACE_FP_RESULT_FPU1 (&ans);
+}
+
+// NEGF.S
+rrrrr,11111100001 + wwwww,10001001000:F_I:::negf_s
+*v850e2v3
+*v850e3v5
+"negf.s r<reg2>, r<reg3>"
+{
+ sim_fpu ans, wop;
+ sim_fpu_status status;
+
+ sim_fpu_32to (&wop, GR[reg2]);
+ TRACE_FP_INPUT_FPU1 (&wop);
+
+ status = sim_fpu_neg (&ans, &wop);
+
+ check_invalid_snan(sd, status, 0);
+
+ sim_fpu_to32 (&GR[reg3], &ans);
+ TRACE_FP_RESULT_FPU1 (&ans);
+}
+
+// NMADDF.S
+rrrrr,111111,RRRRR + wwwww,101,W,10,WWWW,0:F_I:::nmaddf_s
+*v850e2v3
+"nmaddf.s r<reg1>, r<reg2>, r<reg3>, r<reg4>"
+{
+ sim_fpu ans, wop1, wop2, wop3;
+ sim_fpu_status status;
+
+ sim_fpu_32to (&wop1, GR[reg1]);
+ sim_fpu_32to (&wop2, GR[reg2]);
+ sim_fpu_32to (&wop3, GR[reg3]);
+ TRACE_FP_INPUT_FPU3 (&wop1, &wop2, &wop3);
+
+ status = sim_fpu_mul (&ans, &wop1, &wop2);
+ wop1 = ans;
+ status |= sim_fpu_add (&ans, &wop1, &wop3);
+ status |= sim_fpu_round_64 (&ans, FPSR_GET_ROUND(), sim_fpu_denorm_underflow_inexact);
+ wop1 = ans;
+ status |= sim_fpu_neg (&ans, &wop1);
+
+ update_fpsr (sd, status, FPSR_XEV | FPSR_XEI | FPSR_XEO | FPSR_XEU, 0);
+
+ sim_fpu_to32 (&GR[reg4], &ans);
+ TRACE_FP_RESULT_FPU1 (&ans);
+}
+
+// FNMAF.S
+rrrrr,111111,RRRRR + wwwww,10011100100:F_I:::fnmaf_s
+*v850e3v5
+"fnmaf.s r<reg1>, r<reg2>, r<reg3>"
+{
+ sim_fpu ans, wop1, wop2, wop3;
+ sim_fpu_status status;
+
+ sim_fpu_32to (&wop1, GR[reg1]);
+ sim_fpu_32to (&wop2, GR[reg2]);
+ sim_fpu_32to (&wop3, GR[reg3]);
+ TRACE_FP_INPUT_FPU3 (&wop1, &wop2, &wop3);
+
+ status = sim_fpu_mul (&ans, &wop1, &wop2);
+ wop1 = ans;
+ status |= sim_fpu_add (&ans, &wop1, &wop3);
+ status |= sim_fpu_round_64 (&ans, FPSR_GET_ROUND(), sim_fpu_denorm_underflow_inexact);
+ wop1 = ans;
+ status |= sim_fpu_neg (&ans, &wop1);
+
+ update_fpsr (sd, status, FPSR_XEV | FPSR_XEI | FPSR_XEO | FPSR_XEU, 0);
+
+ sim_fpu_to32 (&GR[reg3], &ans);
+ TRACE_FP_RESULT_FPU1 (&ans);
+}
+
+// NMSUBF.S
+rrrrr,111111,RRRRR + wwwww,101,W,11,WWWW,0:F_I:::nmsubf_s
+*v850e2v3
+"nmsubf.s r<reg1>, r<reg2>, r<reg3>, r<reg4>"
+{
+ sim_fpu ans, wop1, wop2, wop3;
+ sim_fpu_status status;
+
+ sim_fpu_32to (&wop1, GR[reg1]);
+ sim_fpu_32to (&wop2, GR[reg2]);
+ sim_fpu_32to (&wop3, GR[reg3]);
+ TRACE_FP_INPUT_FPU3 (&wop1, &wop2, &wop3);
+
+ status = sim_fpu_mul (&ans, &wop1, &wop2);
+ status |= sim_fpu_round_64 (&ans, FPSR_GET_ROUND(), sim_fpu_denorm_underflow_inexact);
+ wop1 = ans;
+ status |= sim_fpu_sub (&ans, &wop1, &wop3);
+ status |= sim_fpu_round_64 (&ans, FPSR_GET_ROUND(), sim_fpu_denorm_underflow_inexact);
+ wop1 = ans;
+ status |= sim_fpu_neg (&ans, &wop1);
+
+ update_fpsr (sd, status, FPSR_XEV | FPSR_XEI | FPSR_XEO | FPSR_XEU, 0);
+
+ sim_fpu_to32 (&GR[reg4], &ans);
+ TRACE_FP_RESULT_FPU1 (&ans);
+}
+
+// FNMSF.S
+rrrrr,111111,RRRRR + wwwww,10011100110:F_I:::fnmsf_s
+*v850e3v5
+"fnmsf.s r<reg1>, r<reg2>, r<reg3>"
+{
+ sim_fpu ans, wop1, wop2, wop3;
+ sim_fpu_status status;
+
+ sim_fpu_32to (&wop1, GR[reg1]);
+ sim_fpu_32to (&wop2, GR[reg2]);
+ sim_fpu_32to (&wop3, GR[reg3]);
+ TRACE_FP_INPUT_FPU3 (&wop1, &wop2, &wop3);
+
+ status = sim_fpu_mul (&ans, &wop1, &wop2);
+ status |= sim_fpu_round_64 (&ans, FPSR_GET_ROUND(), sim_fpu_denorm_underflow_inexact);
+ wop1 = ans;
+ status |= sim_fpu_sub (&ans, &wop1, &wop3);
+ status |= sim_fpu_round_64 (&ans, FPSR_GET_ROUND(), sim_fpu_denorm_underflow_inexact);
+ wop1 = ans;
+ status |= sim_fpu_neg (&ans, &wop1);
+
+ update_fpsr (sd, status, FPSR_XEV | FPSR_XEI | FPSR_XEO | FPSR_XEU, 0);
+
+ sim_fpu_to32 (&GR[reg3], &ans);
+ TRACE_FP_RESULT_FPU1 (&ans);
+}
+
+// RECIPF.D
+rrrr,011111100001 + wwww,010001011110:F_I:::recipf.d
+*v850e2v3
+*v850e3v5
+"recipf.d r<reg2e>, r<reg3e>"
+{
+ sim_fpu ans, wop;
+ sim_fpu_status status;
+
+ sim_fpu_232to (&wop, GR[reg2e+1], GR[reg2e]);
+ TRACE_FP_INPUT_FPU1 (&wop);
+
+ status = sim_fpu_div (&ans, &sim_fpu_one, &wop);
+ status |= sim_fpu_round_64 (&ans, FPSR_GET_ROUND(), sim_fpu_denorm_underflow_inexact);
+
+ update_fpsr (sd, status, FPSR_XEV | FPSR_XEZ | FPSR_XEI | FPSR_XEO | FPSR_XEU, 1);
+
+ sim_fpu_to232 (&GR[reg3e+1], &GR[reg3e], &ans);
+ TRACE_FP_RESULT_FPU1 (&ans);
+}
+
+// RECIPF.S
+rrrrr,11111100001 + wwwww,10001001110:F_I:::recipf.s
+*v850e2v3
+*v850e3v5
+"recipf.s r<reg2>, r<reg3>"
+{
+ sim_fpu ans, wop;
+ sim_fpu_status status;
+
+ sim_fpu_32to (&wop, GR[reg2]);
+ TRACE_FP_INPUT_FPU1 (&wop);
+
+ status = sim_fpu_div (&ans, &sim_fpu_one, &wop);
+ status |= sim_fpu_round_64 (&ans, FPSR_GET_ROUND(), sim_fpu_denorm_underflow_inexact);
+
+ update_fpsr (sd, status, FPSR_XEV | FPSR_XEZ | FPSR_XEI | FPSR_XEO | FPSR_XEU, 0);
+
+ sim_fpu_to32 (&GR[reg3], &ans);
+ TRACE_FP_RESULT_FPU1 (&ans);
+}
+
+// RSQRTF.D
+rrrr,011111100010 + wwww,010001011110:F_I:::rsqrtf.d
+*v850e2v3
+*v850e3v5
+"rsqrtf.d r<reg2e>, r<reg3e>"
+{
+ sim_fpu ans, wop;
+ sim_fpu_status status;
+
+ sim_fpu_232to (&wop, GR[reg2e+1], GR[reg2e]);
+ TRACE_FP_INPUT_FPU1 (&wop);
+
+ status = sim_fpu_sqrt (&ans, &wop);
+ status |= sim_fpu_round_64 (&ans, FPSR_GET_ROUND(), sim_fpu_denorm_underflow_inexact);
+ wop = ans;
+ status = sim_fpu_div (&ans, &sim_fpu_one, &wop);
+ status |= sim_fpu_round_64 (&ans, FPSR_GET_ROUND(), sim_fpu_denorm_underflow_inexact);
+
+ update_fpsr (sd, status, FPSR_XEV | FPSR_XEZ | FPSR_XEI | FPSR_XEO | FPSR_XEU, 1);
+
+ sim_fpu_to232 (&GR[reg3e+1], &GR[reg3e], &ans);
+ TRACE_FP_RESULT_FPU1 (&ans);
+}
+
+// RSQRTF.S
+rrrrr,11111100010 + wwwww,10001001110:F_I:::rsqrtf.s
+*v850e2v3
+*v850e3v5
+"rsqrtf.s r<reg2>, r<reg3>"
+{
+ sim_fpu ans, wop;
+ sim_fpu_status status;
+
+ sim_fpu_32to (&wop, GR[reg2]);
+ TRACE_FP_INPUT_FPU1 (&wop);
+
+ status = sim_fpu_sqrt (&ans, &wop);
+ status |= sim_fpu_round_32 (&ans, FPSR_GET_ROUND(), sim_fpu_denorm_underflow_inexact);
+ wop = ans;
+ status = sim_fpu_div (&ans, &sim_fpu_one, &wop);
+ status |= sim_fpu_round_32 (&ans, FPSR_GET_ROUND(), sim_fpu_denorm_underflow_inexact);
+
+ update_fpsr (sd, status, FPSR_XEV | FPSR_XEZ | FPSR_XEI | FPSR_XEO | FPSR_XEU, 0);
+
+ sim_fpu_to32 (&GR[reg3], &ans);
+ TRACE_FP_RESULT_FPU1 (&ans);
+}
+
+// SQRTF.D
+rrrr,011111100000 + wwww,010001011110:F_I:::sqrtf.d
+*v850e2v3
+*v850e3v5
+"sqrtf.d r<reg2e>, r<reg3e>"
+{
+ sim_fpu ans, wop;
+ sim_fpu_status status;
+
+ sim_fpu_232to (&wop, GR[reg2e+1], GR[reg2e]);
+ TRACE_FP_INPUT_FPU1 (&wop);
+
+ status = sim_fpu_sqrt (&ans, &wop);
+ status |= sim_fpu_round_64 (&ans, FPSR_GET_ROUND(), sim_fpu_denorm_underflow_inexact);
+
+ update_fpsr (sd, status, FPSR_XEV | FPSR_XEI, 1);
+
+ sim_fpu_to232 (&GR[reg3e+1], &GR[reg3e], &ans);
+ TRACE_FP_RESULT_FPU1 (&ans);
+}
+
+// SQRTF.S
+rrrrr,11111100000 + wwwww,10001001110:F_I:::sqrtf.s
+*v850e2v3
+*v850e3v5
+"sqrtf.s r<reg2>, r<reg3>"
+{
+ sim_fpu ans, wop;
+ sim_fpu_status status;
+
+ sim_fpu_32to (&wop, GR[reg2]);
+ TRACE_FP_INPUT_FPU1 (&wop);
+
+ status = sim_fpu_sqrt (&ans, &wop);
+ status |= sim_fpu_round_32 (&ans, FPSR_GET_ROUND(), sim_fpu_denorm_underflow_inexact);
+
+ update_fpsr (sd, status, FPSR_XEV | FPSR_XEI, 0);
+
+ sim_fpu_to32 (&GR[reg3], &ans);
+ TRACE_FP_RESULT_FPU1 (&ans);
+}
+
+// SUBF.D
+rrrr,0111111,RRRR,0 + wwww,010001110010:F_I:::subf.d
+*v850e2v3
+*v850e3v5
+"subf.d r<reg1e>, r<reg2e>, r<reg3e>"
+{
+ sim_fpu ans, wop1, wop2;
+ sim_fpu_status status;
+
+ sim_fpu_232to (&wop1, GR[reg1e+1], GR[reg1e]);
+ sim_fpu_232to (&wop2, GR[reg2e+1], GR[reg2e]);
+ TRACE_FP_INPUT_FPU2 (&wop1, &wop2);
+
+ status = sim_fpu_sub (&ans, &wop2, &wop1);
+ status |= sim_fpu_round_64 (&ans, FPSR_GET_ROUND(), sim_fpu_denorm_underflow_inexact);
+
+ update_fpsr (sd, status, FPSR_XEV | FPSR_XEI | FPSR_XEO | FPSR_XEU, 1);
+
+ sim_fpu_to232 (&GR[reg3e+1], &GR[reg3e], &ans);
+ TRACE_FP_RESULT_FPU1 (&ans);
+}
+
+// SUBF.S
+rrrrr,111111,RRRRR + wwwww,10001100010:F_I:::subf.s
+*v850e2v3
+*v850e3v5
+"subf.s r<reg1>, r<reg2>, r<reg3>"
+{
+ sim_fpu ans, wop1, wop2;
+ sim_fpu_status status;
+
+ sim_fpu_32to (&wop1, GR[reg1]);
+ sim_fpu_32to (&wop2, GR[reg2]);
+ TRACE_FP_INPUT_FPU2 (&wop1, &wop2);
+
+ status = sim_fpu_sub (&ans, &wop2, &wop1);
+ status |= sim_fpu_round_32 (&ans, FPSR_GET_ROUND(), sim_fpu_denorm_underflow_inexact);
+
+ update_fpsr (sd, status, FPSR_XEV | FPSR_XEI | FPSR_XEO | FPSR_XEU, 0);
+
+ sim_fpu_to32 (&GR[reg3], &ans);
+ TRACE_FP_RESULT_FPU1 (&ans);
+}
+
+// TRFSR
+0000011111100000 + 000001000000,bbb,0:F_I:::trfsr
+*v850e2v3
+*v850e3v5
+"trfsr":(bbb == 0)
+"trfsr <bbb>"
+{
+ TRACE_ALU_INPUT1 (GET_FPCC());
+
+ if (TEST_FPCC (bbb))
+ PSW |= PSW_Z;
+ else
+ PSW &= ~PSW_Z;
+
+ TRACE_ALU_RESULT1 (PSW);
+}
+
+// TRNCF.DL
+rrrr,011111100001 + wwww,010001010100:F_I:::trncf_dl
+*v850e2v3
+*v850e3v5
+"trncf.dl r<reg2e>, r<reg3e>"
+{
+ signed64 ans;
+ sim_fpu wop;
+ sim_fpu_status status;
+
+ sim_fpu_232to (&wop, GR[reg2e+1], GR[reg2e]);
+ TRACE_FP_INPUT_FPU1 (&wop);
+
+ status = sim_fpu_to64i (&ans, &wop, sim_fpu_round_zero);
+
+ check_cvt_fi(sd, status, 1);
+
+ GR[reg3e] = ans;
+ GR[reg3e+1] = ans>>32L;
+ TRACE_FP_RESULT_WORD2 (GR[reg3e], GR[reg3e+1]);
+}
+
+// TRNCF.DUL
+rrrr,011111110001 + wwww,010001010100:F_I:::trncf_dul
+*v850e2v3
+*v850e3v5
+"trncf.dul r<reg2e>, r<reg3e>"
+{
+ unsigned64 ans;
+ sim_fpu wop;
+ sim_fpu_status status;
+
+ sim_fpu_232to (&wop, GR[reg2e+1], GR[reg2e]);
+ TRACE_FP_INPUT_FPU1 (&wop);
+
+ status = sim_fpu_to64u (&ans, &wop, sim_fpu_round_zero);
+
+ check_cvt_fi(sd, status, 1);
+
+ GR[reg3e] = ans;
+ GR[reg3e+1] = ans>>32L;
+ TRACE_FP_RESULT_WORD2 (GR[reg3e], GR[reg3e+1]);
+}
+
+// TRNCF.DW
+rrrr,011111100001 + wwwww,10001010000:F_I:::trncf_dw
+*v850e2v3
+*v850e3v5
+"trncf.dw r<reg2e>, r<reg3>"
+{
+ int32 ans;
+ sim_fpu wop;
+ sim_fpu_status status;
+
+ sim_fpu_232to (&wop, GR[reg2e+1], GR[reg2e]);
+ TRACE_FP_INPUT_FPU1 (&wop);
+
+ status = sim_fpu_to32i (&ans, &wop, sim_fpu_round_zero);
+
+ check_cvt_fi(sd, status, 1);
+
+ GR[reg3] = ans;
+ TRACE_FP_RESULT_WORD1 (ans);
+}
+
+// TRNCF.DUW
+rrrr,011111110001 + wwwww,10001010000:F_I:::trncf_duw
+*v850e2v3
+*v850e3v5
+"trncf.duw r<reg2e>, r<reg3>"
+{
+ uint32 ans;
+ sim_fpu wop;
+ sim_fpu_status status;
+
+ sim_fpu_232to (&wop, GR[reg2e+1], GR[reg2e]);
+ TRACE_FP_INPUT_FPU1 (&wop);
+
+ status = sim_fpu_to32u (&ans, &wop, sim_fpu_round_zero);
+
+ check_cvt_fi(sd, status, 1);
+
+ GR[reg3] = ans;
+ TRACE_FP_RESULT_WORD1 (ans);
+}
+
+// TRNCF.SL
+rrrrr,11111100001 + wwww,010001000100:F_I:::trncf_sl
+*v850e2v3
+*v850e3v5
+"trncf.sl r<reg2>, r<reg3e>"
+{
+ signed64 ans;
+ sim_fpu wop;
+ sim_fpu_status status;
+
+ sim_fpu_32to (&wop, GR[reg2]);
+ TRACE_FP_INPUT_FPU1 (&wop);
+
+ status = sim_fpu_to64i (&ans, &wop, sim_fpu_round_zero);
+
+ GR[reg3e] = ans;
+ GR[reg3e+1] = ans >> 32L;
+ TRACE_FP_RESULT_WORD2 (GR[reg3e], GR[reg3e+1]);
+}
+
+// TRNCF.SUL
+rrrrr,11111110001 + wwww,010001000100:F_I:::trncf_sul
+*v850e2v3
+*v850e3v5
+"trncf.sul r<reg2>, r<reg3e>"
+{
+ unsigned64 ans;
+ sim_fpu wop;
+ sim_fpu_status status;
+
+ sim_fpu_32to (&wop, GR[reg2]);
+ TRACE_FP_INPUT_FPU1 (&wop);
+
+ status = sim_fpu_to64u (&ans, &wop, sim_fpu_round_zero);
+
+ GR[reg3e] = ans;
+ GR[reg3e+1] = ans >> 32L;
+ TRACE_FP_RESULT_WORD2 (GR[reg3e], GR[reg3e+1]);
+}
+
+// TRNCF.SW
+rrrrr,11111100001 + wwwww,10001000000:F_I:::trncf_sw
+*v850e2v3
+*v850e3v5
+"trncf.sw r<reg2>, r<reg3>"
+{
+ int32 ans;
+ sim_fpu wop;
+ sim_fpu_status status;
+
+ sim_fpu_32to (&wop, GR[reg2]);
+ TRACE_FP_INPUT_FPU1 (&wop);
+
+ status = sim_fpu_to32i (&ans, &wop, sim_fpu_round_zero);
+
+ check_cvt_fi(sd, status, 0);
+
+ GR[reg3] = ans;
+ TRACE_FP_RESULT_WORD1 (ans);
+}
+
+// TRNCF.SUW
+rrrrr,11111110001 + wwwww,10001000000:F_I:::trncf_suw
+*v850e2v3
+*v850e3v5
+"trncf.suw r<reg2>, r<reg3>"
+{
+ uint32 ans;
+ sim_fpu wop;
+ sim_fpu_status status;
+
+ sim_fpu_32to (&wop, GR[reg2]);
+ TRACE_FP_INPUT_FPU1 (&wop);
+
+ status = sim_fpu_to32u (&ans, &wop, sim_fpu_round_zero);
+
+ check_cvt_fi(sd, status, 0);
+
+ GR[reg3] = ans;
+ TRACE_FP_RESULT_WORD1 (ans);
+}
+
+// ROTL
+rrrrr,111111,iiiii+wwwww,00011000100:VII:::rotl_imm
+*v850e3v5
+"rotl imm5, r<reg2>, r<reg3>"
+{
+ TRACE_ALU_INPUT1 (GR[reg2]);
+ v850_rotl (sd, imm5, GR[reg2], & GR[reg3]);
+ TRACE_ALU_RESULT1 (GR[reg3]);
+}
+
+rrrrr,111111,RRRRR+wwwww,00011000110:VII:::rotl
+*v850e3v5
+"rotl r<reg1>, r<reg2>, r<reg3>"
+{
+ TRACE_ALU_INPUT2 (GR[reg1], GR[reg2]);
+ v850_rotl (sd, GR[reg1], GR[reg2], & GR[reg3]);
+ TRACE_ALU_RESULT1 (GR[reg3]);
+}
+
+// BINS
+rrrrr,111111,RRRRR+bbbb,B,0001001,BBB,0:IX:::bins_top
+*v850e3v5
+"bins r<reg1>, <bit13> + 16, <bit4> - <bit13> + 17, r<reg2>"
+{
+ TRACE_ALU_INPUT1 (GR[reg1]);
+ v850_bins (sd, GR[reg1], bit13 + 16, bit4 + 16, & GR[reg2]);
+ TRACE_ALU_RESULT1 (GR[reg2]);
+}
+
+rrrrr,111111,RRRRR+bbbb,B,0001011,BBB,0:IX:::bins_middle
+*v850e3v5
+"bins r<reg1>, <bit13>, <bit4> - <bit13> + 17, r<reg2>"
+{
+ TRACE_ALU_INPUT1 (GR[reg1]);
+ v850_bins (sd, GR[reg1], bit13, bit4 + 16, & GR[reg2]);
+ TRACE_ALU_RESULT1 (GR[reg2]);
+}
+
+rrrrr,111111,RRRRR+bbbb,B,0001101,BBB,0:IX:::bins_bottom
+*v850e3v5
+"bins r<reg1>, <bit13>, <bit4> - <bit13> + 1, r<reg2>"
+{
+ TRACE_ALU_INPUT1 (GR[reg1]);
+ v850_bins (sd, GR[reg1], bit13, bit4, & GR[reg2]);
+ TRACE_ALU_RESULT1 (GR[reg2]);
+}
+
+vvvvv,11111100100+xxxxx,11001111110:C:::cnvq15q30
+*v850e3v5
+"cnvq15q30 v<vreg2>, v<vreg3>"
+{
+ reg64_t v;
+
+ TRACE_ALU_INPUT1 (VR[vreg2]);
+
+ if (VR[vreg2] & (1 << 15))
+ v = 0x0001ffffffff0000 | VR[vreg2];
+ else
+ v = VR[vreg2];
+ VR[vreg3] = v << 15;
+
+ TRACE_ALU_RESULT1 (VR[vreg3]);
+}
+
+vvvvv,11111100110+xxxxx,11001111110:C:::cnvq30q15
+*v850e3v5
+"cnvq30q15 v<vreg2>, v<vreg3>"
+{
+ reg64_t v;
+
+ TRACE_ALU_INPUT1 (VR[vreg2]);
+
+ v = ROUND_Q62_Q15 (VR[vreg2]);
+ SAT16 (v);
+ VR[vreg3] &= 0xffffffffffff0000UL;
+ v &= 0xffffUL;
+ VR[vreg3] |= v;
+
+ TRACE_ALU_RESULT1 (VR[vreg3]);
+}
+
+vvvvv,11111100101+xxxxx,11001111110:C:::cnvq31q62
+*v850e3v5
+"cnvq31q62 v<vreg2>, v<vreg3>"
+{
+ reg64_t v;
+
+ TRACE_ALU_INPUT1 (VR[vreg2]);
+
+ if (VR[vreg2] & (1 << 31))
+ v = 0xffffffff00000000 | VR[vreg2];
+ else
+ v = VR[vreg2];
+ VR[vreg3] = v << 31;
+
+ TRACE_ALU_RESULT1 (VR[vreg3]);
+}
+
+vvvvv,11111100111+xxxxx,11001111110:C:::cnvq62q31
+*v850e3v5
+"cnvq62q31 v<vreg2>, v<vreg3>"
+{
+ reg64_t v;
+
+ TRACE_ALU_INPUT1 (VR[vreg2]);
+
+ v = ROUND_Q62_Q31 (VR[vreg2]);
+ SAT32 (v);
+ VR[vreg3] &= 0xffffffff00000000UL;
+ v &= 0xffffffffUL;
+ VR[vreg3] |= v;
+
+ TRACE_ALU_RESULT1 (VR[vreg3]);
+}
+
+vvvvv,111111100,ii+xxxxx,11011011100:C:::dup.h
+*v850e3v5
+"dup.h <imm2> v<vreg2>, v<vreg3>"
+{
+ reg64_t v;
+
+ TRACE_ALU_INPUT1 (VR[vreg2]);
+ switch (imm2)
+ {
+ case 0: v = VR[vreg2] & 0xffff; break;
+ case 1: v = (VR[vreg2] >> 16) & 0xffff; break;
+ case 2: v = (VR[vreg2] >> 32) & 0xffff; break;
+ case 3: v = (VR[vreg2] >> 48) & 0xffff; break;
+ default:
+ sim_engine_halt (SD, CPU, NULL, cia, sim_signalled, SIM_SIGILL);
+ v = 0;
+ }
+
+ VR[vreg3] = v | (v << 16) | (v << 32) | (v << 48);
+ TRACE_ALU_RESULT1 (VR[vreg3]);
+}
+
+vvvvv,1111111100,i+xxxxx,11011011110:C:::dup.w
+*v850e3v5
+"dup.w <imm1> v<vreg2>, v<vreg3>"
+{
+ reg64_t v;
+
+ TRACE_ALU_INPUT1 (VR[vreg2]);
+ switch (imm1)
+ {
+ case 0: v = VR[vreg2] & 0xffffffff; break;
+ case 1: v = (VR[vreg2] >> 32) & 0xffffffff; break;
+ default:
+ sim_engine_halt (SD, CPU, NULL, cia, sim_signalled, SIM_SIGILL);
+ v = 0;
+ }
+
+ VR[vreg3] = v | (v << 32);
+ TRACE_ALU_RESULT1 (VR[vreg3]);
+}
+
+vvvvv,11111101000+xxxxx,11001111110:C:::expq31
+*v850e3v5
+"expq31 v<vreg2>, v<vreg3>"
+{
+ int i;
+ reg64_t v;
+
+ TRACE_ALU_INPUT1 (VR[vreg2]);
+ v = VR[vreg2] & 0xffffffff;
+ if (v & (1 << 31))
+ {
+ if (v == 0x80000000)
+ i = 31;
+ else if (v == 0xffffffff)
+ i = 0;
+ else
+ for (i = 31; i; --i)
+ if ((v & (1 << i)) == 0)
+ break;
+ }
+ else
+ {
+ if (v == 0x7fffffff)
+ i = 31;
+ else if (v == 0x0)
+ i = 0;
+ else
+ for (i = 31; i; --i)
+ if (v & (1 << i))
+ break;
+ }
+ VR[vreg3] = 31 - i;
+ TRACE_ALU_RESULT1 (VR[vreg3]);
+}
+
+rrrr,011111100000+0000011011011000:C:::modadd
+*v850e3v5
+"modadd r<reg2e>"
+{
+ reg_t r;
+ int32 inc;
+ reg_t max;
+
+ TRACE_ALU_INPUT1 (GR[reg2e]);
+ r = GR[reg2e];
+ inc = r >> 16;
+ r = r & 0xffff;
+ max = GR[reg2e + 1];
+ max &= 0xffff;
+ r += inc;
+ if (inc > 0 && r > max)
+ r = 0;
+ else if (inc < 0 && r < 0)
+ r = max;
+ GR[reg2e] = (r & 0xffff) | (inc << 16);
+ TRACE_ALU_RESULT1 (GR[reg2e]);
+}
+
+vvvvv,11111111000+wwwww,11011011010:C:::mov_dw_to_gr
+*v850e3v5
+"mov.dw v<vreg2>, r<reg3>"
+{
+ TRACE_ALU_INPUT1 (VR[vreg2]);
+ GR[reg3] = VR[vreg2] & 0xffffffff;
+ GR[reg3 + 1] = VR[vreg2] >> 32;
+ TRACE_ALU_RESULT2 (GR[reg3], GR[reg3 + 1]);
+}
+
+rrrrr,11111111100+xxxxx,11011011010:C:::mov_dw_to_vr
+*v850e3v5
+"mov.dw r<reg2>, v<vreg3>"
+{
+ TRACE_ALU_INPUT2 (GR[reg2], GR[reg2 + 1]);
+ VR[vreg3] = GR[reg2 + 1];
+ VR[vreg3] <<= 32;
+ VR[vreg3] |= GR[reg2];
+ TRACE_ALU_RESULT1 (VR[vreg3]);
+}
+
+vvvvv,111111000,ii+xxxxx,11011011100:C:::mov.h
+*v850e3v5
+"mov.h <imm2> v<vreg2>, v<vreg3>"
+{
+ reg64_t v = VR[vreg2];
+ reg64_t mask = 0xffffUL;
+ int shift;
+
+ TRACE_ALU_INPUT1 (VR[vreg2]);
+
+ switch (imm2)
+ {
+ default:
+ sim_engine_halt (SD, CPU, NULL, cia, sim_signalled, SIM_SIGILL);
+ case 0: shift = 0; break;
+ case 1: shift = 16; break;
+ case 2: shift = 32; break;
+ case 3: shift = 48; break;
+ }
+
+ v &= mask;
+ VR[vreg3] &= ~ (mask << shift);
+ VR[vreg3] |= (v << shift);
+
+ TRACE_ALU_RESULT1 (VR[vreg3]);
+}
+
+vvvvv,1111110000,i+xxxxx,11011011010:C:::mov.w.vreg_to_vreg
+*v850e3v5
+"mov.w <imm1> v<vreg2>, v<vreg3>"
+{
+ reg64_t v = VR[vreg2];
+ reg64_t mask = 0xffffffffUL;
+ int shift;
+
+ TRACE_ALU_INPUT1 (VR[vreg2]);
+ switch (imm1)
+ {
+ default:
+ sim_engine_halt (SD, CPU, NULL, cia, sim_signalled, SIM_SIGILL);
+ case 0: shift = 0; break;
+ case 1: shift = 32; break;
+ }
+
+ v &= mask;
+ VR[vreg3] &= ~ (mask << shift);
+ VR[vreg3] |= (v << shift);
+
+ TRACE_ALU_RESULT1 (VR[vreg3]);
+}
+
+rrrrr,1111111000,i+xxxxx,11011011010:C:::mov.w.reg_to_vreg
+*v850e3v5
+"mov.w <imm1> r<reg2>, v<vreg3>"
+{
+ reg64_t v;
+ reg64_t mask = 0xffffffffUL;
+ int shift;
+
+ TRACE_ALU_INPUT1 (GR[reg2]);
+ switch (imm1)
+ {
+ default:
+ sim_engine_halt (SD, CPU, NULL, cia, sim_signalled, SIM_SIGILL);
+ case 0: shift = 0; break;
+ case 1: shift = 32; break;
+ }
+
+ v = GR[reg2];
+ VR[vreg3] &= ~ (mask << shift);
+ VR[vreg3] |= (v << shift);
+
+ TRACE_ALU_RESULT1 (VR[vreg3]);
+}
+
+vvvvv,1111110100,i+wwwww,11011011010:C:::mov.w.vreg_to_reg
+*v850e3v5
+"mov.w <imm1> v<vreg2>, r<reg3>"
+{
+ TRACE_ALU_INPUT1 (VR[vreg2]);
+
+ switch (imm1)
+ {
+ default:
+ sim_engine_halt (SD, CPU, NULL, cia, sim_signalled, SIM_SIGILL);
+ case 0:
+ GR[reg3] = VR[vreg2];
+ break;
+ case 1:
+ GR[reg3] = VR[vreg2] >> 32;
+ break;
+ }
+
+ TRACE_ALU_RESULT1 (GR[reg3]);
+}
+
+vvvvv,111111,VVVVV+xxxxx,11001101010:C:::pki16i32
+*v850e3v5
+"pki16i32 v<vreg1>, v<vreg2>, v<vreg3>"
+{
+ reg64_t v,t;
+
+ TRACE_ALU_INPUT1 (VR[vreg1]);
+
+ v = VR[vreg1];
+ VR[vreg2] = (SEXT32 (v, 16) & 0xffffffff);
+ v >>= 16;
+ t = SEXT32 (v, 16);
+ VR[vreg2] |= t << 32;
+
+ v >>= 16;
+ VR[vreg3] = (SEXT32 (v, 16) & 0xffffffff);
+ v >>= 16;
+ t = SEXT32 (v, 16);
+ VR[vreg3] |= t << 32;
+
+ TRACE_ALU_RESULT2 (VR[vreg2], VR[vreg3]);
+}
+
+vvvvv,111111,VVVVV+xxxxx,11001100110:C:::pki16ui8
+*v850e3v5
+"pki16ui8 v<vreg1>, v<vreg2>, v<vreg3>"
+{
+ TRACE_ALU_INPUT2 (VR[vreg1], VR[vreg2]);
+
+ VR[vreg3] = VR[vreg1] & 0xff;
+ VR[vreg3] |= ((VR[vreg1] >> 8) & 0xff00);
+ VR[vreg3] |= ((VR[vreg1] >> 16) & 0xff0000);
+ VR[vreg3] |= ((VR[vreg1] >> 24) & 0xff000000);
+
+ VR[vreg3] |= ((VR[vreg2] << 32) & 0xff00000000UL);
+ VR[vreg3] |= ((VR[vreg2] << 24) & 0xff0000000000UL);
+ VR[vreg3] |= ((VR[vreg2] << 16) & 0xff000000000000UL);
+ VR[vreg3] |= ((VR[vreg2] << 8) & 0xff00000000000000UL);
+
+ TRACE_ALU_RESULT1 (VR[vreg3]);
+}
+
+vvvvv,111111,VVVVV+xxxxx,11001100100:C:::pki32i16
+*v850e3v5
+"pki32i16 v<vreg1>, v<vreg2>, v<vreg3>"
+{
+ reg64_t v;
+
+ TRACE_ALU_INPUT2 (VR[vreg1], VR[vreg2]);
+
+ v = VR[vreg1] & 0xffffffff;
+ SAT16 (v);
+ VR[vreg3] = v & 0xffff;
+
+ v = VR[vreg1] >> 32;
+ SAT16 (v);
+ VR[vreg3] |= ((v & 0xffff) << 16);
+
+ v = VR[vreg2] & 0xffffffff;
+ SAT16 (v);
+ VR[vreg3] = ((v & 0xffff) << 32);
+
+ v = VR[vreg2] >> 32;
+ SAT16 (v);
+ VR[vreg3] |= ((v & 0xffff) << 48);
+
+ TRACE_ALU_RESULT1 (VR[vreg3]);
+}
+
+vvvvv,111111,VVVVV+xxxxx,11001100010:C:::pki64i32
+*v850e3v5
+"pki64i32 v<vreg1>, v<vreg2>, v<vreg3>"
+{
+ reg64_t v;
+
+ TRACE_ALU_INPUT2 (VR[vreg1], VR[vreg2]);
+
+ v = VR[vreg1];
+ SAT32 (v);
+ VR[vreg3] = v & 0xffffffff;
+
+ v = VR[vreg2];
+ SAT32 (v);
+ VR[vreg3] |= v << 32;
+
+ TRACE_ALU_RESULT1 (VR[vreg3]);
+}
+
+vvvvv,111111,VVVVV+xxxxx,11001101000:C:::pkq15q31
+*v850e3v5
+"pkq15q31 v<vreg1>, v<vreg2>, v<vreg3>"
+{
+ reg64_t v;
+
+ TRACE_ALU_INPUT1 (VR[vreg1]);
+
+ v = VR[vreg1];
+ VR[vreg2] = ((v & 0xffff) << 16);
+ VR[vreg2] |= ((v & 0xffff0000) << 32);
+
+ VR[vreg3] = ((v & 0xffff00000000UL) >> 16);
+ VR[vreg3] |= ((v & 0xffff000000000000UL));
+
+ TRACE_ALU_RESULT2 (VR[vreg2], VR[vreg3]);
+}
+
+vvvvv,111111,VVVVV+xxxxx,11001011110:C:::pkq30q31
+*v850e3v5
+"pkq30q31 v<vreg1>, v<vreg2>, v<vreg3>"
+{
+ reg64_t v;
+
+ TRACE_ALU_INPUT2 (VR[vreg1], VR[vreg2]);
+
+ v = VR[vreg1];
+ v <<= 1;
+ SAT32 (v);
+ VR[vreg3] = v & 0xffffffff;
+
+ v = VR[vreg2];
+ v <<= 1;
+ SAT32 (v);
+ VR[vreg3] = v << 32;
+
+ TRACE_ALU_RESULT1 (VR[vreg3]);
+}
+
+vvvvv,111111,VVVVV+xxxxx,11001100000:C:::pkq31q15
+*v850e3v5
+"pkq31q15 v<vreg1>, v<vreg2>, v<vreg3>"
+{
+ reg64_t v;
+
+ TRACE_ALU_INPUT2 (VR[vreg1], VR[vreg2]);
+
+ v = ROUND_Q31_Q15 (VR[vreg1] & 0xffffffff);
+ SAT16 (v);
+ VR[vreg3] = v & 0xffff;
+
+ v = ROUND_Q31_Q15 (VR[vreg1] >> 32);
+ SAT16 (v);
+ VR[vreg3] |= (v & 0xffff) << 16;
+
+ v = ROUND_Q31_Q15 (VR[vreg2] & 0xffffffff);
+ SAT16 (v);
+ VR[vreg3] |= (v & 0xffff) << 32;
+
+ v = ROUND_Q31_Q15 (VR[vreg2] >> 32);
+ SAT16 (v);
+ VR[vreg3] |= (v & 0xffff) << 48;
+
+ TRACE_ALU_RESULT1 (VR[vreg3]);
+}
+
+vvvvv,111111,VVVVV+xxxxx,11001101100:C:::pkui8i16
+*v850e3v5
+"pkui8i16 v<vreg1>, v<vreg2>, v<vreg3>"
+{
+ reg64_t v;
+
+ TRACE_ALU_INPUT1 (VR[vreg1]);
+
+ v = VR[vreg1];
+
+ VR[vreg2] = v & 0x00ff;
+ VR[vreg2] |= (v << 8) & 0x00ff0000;
+ VR[vreg2] |= (v << 16) & 0x00ff00000000UL;
+ VR[vreg2] |= (v << 24) & 0x00ff000000000000UL;
+
+ VR[vreg3] = (v >> 32) & 0x00ff;
+ VR[vreg3] |= (v >> 24) & 0x00ff0000;
+ VR[vreg3] |= (v >> 16) & 0x00ff00000000UL;
+ VR[vreg3] |= (v >> 8) & 0x00ff000000000000UL;
+
+ TRACE_ALU_RESULT2 (VR[vreg2], VR[vreg3]);
+}
+
+vvvvv,11111100000+xxxxx,11001111110:C:::vabs.h
+*v850e3v5
+"vabs.h v<vreg2>, v<vreg3>"
+{
+ int shift;
+
+ TRACE_ALU_INPUT1 (VR[vreg2]);
+
+ VR[vreg3] = 0;
+ for (shift = 0; shift < 64; shift += 16);
+ {
+ reg64_t v;
+
+ v = VR[vreg2] >> shift;
+ ABS16 (v);
+ VR[vreg3] |= v << shift;
+ }
+
+ TRACE_ALU_RESULT1 (VR[vreg3]);
+}
+
+vvvvv,11111100001+xxxxx,11001111110:C:::vabs.w
+*v850e3v5
+"vabs.w v<vreg2>, v<vreg3>"
+{
+ reg64_t v;
+
+ TRACE_ALU_INPUT1 (VR[vreg2]);
+
+ v = VR[vreg2];
+ ABS32 (v);
+ VR[vreg3] = v;
+
+ v = VR[vreg2] >> 32;
+ ABS32 (v);
+ VR[vreg3] |= v << 32;
+
+ TRACE_ALU_RESULT1 (VR[vreg3]);
+}
+
+vvvvv,111111,VVVVV+xxxxx,11001011000:C:::vadd.dw
+*v850e3v5
+"vadd.dw v<vreg1>, v<vreg2>, v<vreg3>"
+{
+ TRACE_ALU_INPUT2 (VR[vreg1], VR[vreg2]);
+
+ /* FIXME: saturation handling needed. */
+ sim_engine_halt (SD, CPU, NULL, cia, sim_signalled, SIM_SIGILL);
+
+ VR[vreg3] = VR[vreg1] + VR[vreg2];
+
+ TRACE_ALU_RESULT1 (VR[vreg3]);
+}
+
+vvvvv,111111,VVVVV+xxxxx,11000000000:C:::vadd.h
+*v850e3v5
+"vadd.h v<vreg1>, v<vreg2>, v<vreg3>"
+{
+ TRACE_ALU_INPUT2 (VR[vreg1], VR[vreg2]);
+
+ /* FIXME: Implementation needed. */
+ sim_engine_halt (SD, CPU, NULL, cia, sim_signalled, SIM_SIGILL);
+
+ TRACE_ALU_RESULT1 (VR[vreg3]);
+}
+
+vvvvv,111111,VVVVV+xxxxx,11000000010:C:::vadd.w
+*v850e3v5
+"vadd.w v<vreg1>, v<vreg2>, v<vreg3>"
+{
+ TRACE_ALU_INPUT2 (VR[vreg1], VR[vreg2]);
+
+ /* FIXME: Implementation needed. */
+ sim_engine_halt (SD, CPU, NULL, cia, sim_signalled, SIM_SIGILL);
+
+ TRACE_ALU_RESULT1 (VR[vreg3]);
+}
+
+vvvvv,111111,VVVVV+xxxxx,11000001000:C:::vadds.h
+*v850e3v5
+"vadds.h v<vreg1>, v<vreg2>, v<vreg3>"
+{
+ TRACE_ALU_INPUT2 (VR[vreg1], VR[vreg2]);
+
+ /* FIXME: Implementation needed. */
+ sim_engine_halt (SD, CPU, NULL, cia, sim_signalled, SIM_SIGILL);
+
+ TRACE_ALU_RESULT1 (VR[vreg3]);
+}
+
+vvvvv,111111,VVVVV+xxxxx,11000001010:C:::vadds.w
+*v850e3v5
+"vadds.w v<vreg1>, v<vreg2>, v<vreg3>"
+{
+ TRACE_ALU_INPUT2 (VR[vreg1], VR[vreg2]);
+
+ /* FIXME: Implementation needed. */
+ sim_engine_halt (SD, CPU, NULL, cia, sim_signalled, SIM_SIGILL);
+
+ TRACE_ALU_RESULT1 (VR[vreg3]);
+}
+
+vvvvv,111111,VVVVV+xxxxx,11000010000:C:::vaddsat.h
+*v850e3v5
+"vaddsat.h v<vreg1>, v<vreg2>, v<vreg3>"
+{
+ TRACE_ALU_INPUT2 (VR[vreg1], VR[vreg2]);
+
+ /* FIXME: Implementation needed. */
+ sim_engine_halt (SD, CPU, NULL, cia, sim_signalled, SIM_SIGILL);
+
+ TRACE_ALU_RESULT1 (VR[vreg3]);
+}
+
+vvvvv,111111,VVVVV+xxxxx,11000010010:C:::vaddsat.w
+*v850e3v5
+"vaddsat.w v<vreg1>, v<vreg2>, v<vreg3>"
+{
+ TRACE_ALU_INPUT2 (VR[vreg1], VR[vreg2]);
+
+ /* FIXME: Implementation needed. */
+ sim_engine_halt (SD, CPU, NULL, cia, sim_signalled, SIM_SIGILL);
+
+ TRACE_ALU_RESULT1 (VR[vreg3]);
+}
+
+vvvvv,111111,VVVVV+xxxxx,11010000000:C:::vand
+*v850e3v5
+"vand v<vreg1>, v<vreg2>, v<vreg3>"
+{
+ TRACE_ALU_INPUT2 (VR[vreg1], VR[vreg2]);
+
+ VR[vreg3] = VR[vreg1] & VR[vreg2];
+
+ TRACE_ALU_RESULT1 (VR[vreg3]);
+}
+
+vvvvv,111111,VVVVV+xxxxx,11001011100:C:::vbiq.h
+*v850e3v5
+"vbiq.h v<vreg1>, v<vreg2>, v<vreg3>"
+{
+ TRACE_ALU_INPUT2 (VR[vreg1], VR[vreg2]);
+
+ /* FIXME: Implementation needed. */
+ sim_engine_halt (SD, CPU, NULL, cia, sim_signalled, SIM_SIGILL);
+
+ TRACE_ALU_RESULT2 (VR[vreg2], VR[vreg3]);
+}
+
+vvvvv,11111100111+xxxxx,11011011110:C:::vbswap.dw
+*v850e3v5
+"vbswap.dw v<vreg2>, v<vreg3>"
+{
+ TRACE_ALU_INPUT1 (VR[vreg2]);
+
+ /* FIXME: Implementation needed. */
+ sim_engine_halt (SD, CPU, NULL, cia, sim_signalled, SIM_SIGILL);
+
+ TRACE_ALU_RESULT1 (VR[vreg3]);
+}
+
+vvvvv,11111100101+xxxxx,11011011110:C:::vbswap.h
+*v850e3v5
+"vbswap.h v<vreg2>, v<vreg3>"
+{
+ TRACE_ALU_INPUT1 (VR[vreg2]);
+
+ /* FIXME: Implementation needed. */
+ sim_engine_halt (SD, CPU, NULL, cia, sim_signalled, SIM_SIGILL);
+
+ TRACE_ALU_RESULT1 (VR[vreg3]);
+}
+
+vvvvv,11111100110+xxxxx,11011011110:C:::vbswap.w
+*v850e3v5
+"vbswap.w v<vreg2>, v<vreg3>"
+{
+ TRACE_ALU_INPUT1 (VR[vreg2]);
+
+ /* FIXME: Implementation needed. */
+ sim_engine_halt (SD, CPU, NULL, cia, sim_signalled, SIM_SIGILL);
+
+ TRACE_ALU_RESULT1 (VR[vreg3]);
+}
+
+vvvvv,111111,VVVVV+xxxxx,11001110000:C:::vcalc.h
+*v850e3v5
+"vcalc.h v<vreg1>,v<vreg2>, v<vreg3>"
+{
+ TRACE_ALU_INPUT2 (VR[vreg1], VR[vreg2]);
+
+ /* FIXME: Implementation needed. */
+ sim_engine_halt (SD, CPU, NULL, cia, sim_signalled, SIM_SIGILL);
+
+ TRACE_ALU_RESULT1 (VR[vreg3]);
+}
+
+vvvvv,111111,VVVVV+xxxxx,11001110010:C:::vcalc.w
+*v850e3v5
+"vcalc.w v<vreg1>,v<vreg2>, v<vreg3>"
+{
+ TRACE_ALU_INPUT2 (VR[vreg1], VR[vreg2]);
+
+ /* FIXME: Implementation needed. */
+ sim_engine_halt (SD, CPU, NULL, cia, sim_signalled, SIM_SIGILL);
+
+ TRACE_ALU_RESULT1 (VR[vreg3]);
+}
+
+vvvvv,111111,VVVVV+xxxxx,11010110000:C:::vcmov
+*v850e3v5
+"vcmov v<vreg1>, v<vreg2>, v<vreg3>"
+{
+ TRACE_ALU_INPUT2 (VR[vreg1], VR[vreg2]);
+
+ /* FIXME: Implementation needed. */
+ sim_engine_halt (SD, CPU, NULL, cia, sim_signalled, SIM_SIGILL);
+
+ TRACE_ALU_RESULT1 (VR[vreg3]);
+}