phy: exynos5-usbdrd: Add pipe-clk, utmi-clk and itp-clk support

[deliverable/linux.git] / Documentation / devicetree / bindings / phy / samsung-phy.txt

diff --git a/Documentation/devicetree/bindings/phy/samsung-phy.txt b/Documentation/devicetree/bindings/phy/samsung-phy.txt
index 15e0f2c7130f253698403877b55029334bc87400..d5bad920827fa86d1e503aca649644bbf44cd8a4 100644 (file)
--- a/Documentation/devicetree/bindings/phy/samsung-phy.txt
+++ b/Documentation/devicetree/bindings/phy/samsung-phy.txt
@@ -128,6 +128,7 @@ Required properties:
 - compatible : Should be set to one of the following supported values:
        - "samsung,exynos5250-usbdrd-phy" - for exynos5250 SoC,
        - "samsung,exynos5420-usbdrd-phy" - for exynos5420 SoC.
+       - "samsung,exynos7-usbdrd-phy" - for exynos7 SoC.
 - reg : Register offset and length of USB DRD PHY register set;
 - clocks: Clock IDs array as required by the controller
 - clock-names: names of clocks correseponding to IDs in the clock property;
@@ -138,6 +139,11 @@ Required properties:
               PHY operations, associated by phy name. It is used to
               determine bit values for clock settings register.
               For Exynos5420 this is given as 'sclk_usbphy30' in CMU.
+       - optional clocks: Exynos7 SoC has now following additional
+                          gate clocks available:
+                          - phy_pipe: for PIPE3 phy
+                          - phy_utmi: for UTMI+ phy
+                          - itp: for ITP generation
 - samsung,pmu-syscon: phandle for PMU system controller interface, used to
                      control pmu registers for power isolation.
 - #phy-cells : from the generic PHY bindings, must be 1;