powerpc/sysdev: implement FSL GTM support

[deliverable/linux.git] / Documentation / powerpc / booting-without-of.txt

diff --git a/Documentation/powerpc/booting-without-of.txt b/Documentation/powerpc/booting-without-of.txt
index 1d2a772506cfa46e23acda9c3660369b72e1e85f..8675ebca2cfd417f24930439a56cec110f21d256 100644 (file)
--- a/Documentation/powerpc/booting-without-of.txt
+++ b/Documentation/powerpc/booting-without-of.txt
@@ -57,7 +57,11 @@ Table of Contents
       n) 4xx/Axon EMAC ethernet nodes
       o) Xilinx IP cores
       p) Freescale Synchronous Serial Interface
-         q) USB EHCI controllers
+      q) USB EHCI controllers
+      r) Freescale Display Interface Unit
+      s) Freescale on board FPGA
+      t) Freescael MSI interrupt controller
+      u) Freescale General-purpose Timers Module
 
   VII - Marvell Discovery mv64[345]6x System Controller chips
     1) The /system-controller node
@@ -1360,14 +1364,11 @@ platforms are moved over to use the flattened-device-tree model.
 
        pic@40000 {
                linux,phandle = <40000>;
-               clock-frequency = <0>;
                interrupt-controller;
                #address-cells = <0>;
                reg = <40000 40000>;
-               built-in;
                compatible = "chrp,open-pic";
                device_type = "open-pic";
-               big-endian;
        };
 
 
@@ -2870,6 +2871,75 @@ platforms are moved over to use the flattened-device-tree model.
                reg = <0xe8000000 32>;
        };
 
+    t) Freescale MSI interrupt controller
+
+    Reguired properities:
+    - compatible : compatible list, contains 2 entries,
+      first is "fsl,CHIP-msi", where CHIP is the processor(mpc8610, mpc8572,
+      etc.) and the second is "fsl,mpic-msi" or "fsl,ipic-msi" depending on
+      the parent type.
+    - reg : should contain the address and the length of the shared message
+      interrupt register set.
+    - msi-available-ranges: use <start count> style section to define which
+      msi interrupt can be used in the 256 msi interrupts. This property is
+      optional, without this, all the 256 MSI interrupts can be used.
+    - interrupts : each one of the interrupts here is one entry per 32 MSIs,
+      and routed to the host interrupt controller. the interrupts should
+      be set as edge sensitive.
+    - interrupt-parent: the phandle for the interrupt controller
+      that services interrupts for this device. for 83xx cpu, the interrupts
+      are routed to IPIC, and for 85xx/86xx cpu the interrupts are routed
+      to MPIC.
+
+    Example
+       msi@41600 {
+               compatible = "fsl,mpc8610-msi", "fsl,mpic-msi";
+               reg = <0x41600 0x80>;
+               msi-available-ranges = <0 0x100>;
+               interrupts = <
+                       0xe0 0
+                       0xe1 0
+                       0xe2 0
+                       0xe3 0
+                       0xe4 0
+                       0xe5 0
+                       0xe6 0
+                       0xe7 0>;
+               interrupt-parent = <&mpic>;
+       };
+
+    u) Freescale General-purpose Timers Module
+
+    Required properties:
+      - compatible : should be
+        "fsl,<chip>-gtm", "fsl,gtm" for SOC GTMs
+        "fsl,<chip>-qe-gtm", "fsl,qe-gtm", "fsl,gtm" for QE GTMs
+        "fsl,<chip>-cpm2-gtm", "fsl,cpm2-gtm", "fsl,gtm" for CPM2 GTMs
+      - reg : should contain gtm registers location and length (0x40).
+      - interrupts : should contain four interrupts.
+      - interrupt-parent : interrupt source phandle.
+      - clock-frequency : specifies the frequency driving the timer.
+
+    Example:
+
+    timer@500 {
+       compatible = "fsl,mpc8360-gtm", "fsl,gtm";
+       reg = <0x500 0x40>;
+       interrupts = <90 8 78 8 84 8 72 8>;
+       interrupt-parent = <&ipic>;
+       /* filled by u-boot */
+       clock-frequency = <0>;
+    };
+
+    timer@440 {
+       compatible = "fsl,mpc8360-qe-gtm", "fsl,qe-gtm", "fsl,gtm";
+       reg = <0x440 0x40>;
+       interrupts = <12 13 14 15>;
+       interrupt-parent = <&qeic>;
+       /* filled by u-boot */
+       clock-frequency = <0>;
+    };
+
 VII - Marvell Discovery mv64[345]6x System Controller chips
 ===========================================================
 
@@ -3622,14 +3692,11 @@ not necessary as they are usually the same as the root node.
 
                pic@40000 {
                        linux,phandle = <40000>;
-                       clock-frequency = <0>;
                        interrupt-controller;
                        #address-cells = <0>;
                        reg = <40000 40000>;
-                       built-in;
                        compatible = "chrp,open-pic";
                        device_type = "open-pic";
-                        big-endian;
                };
 
                i2c@3000 {