menu "ARC Platform/SoC/Board"
-source "arch/arc/plat-arcfpga/Kconfig"
+source "arch/arc/plat-sim/Kconfig"
source "arch/arc/plat-tb10x/Kconfig"
+source "arch/arc/plat-axs10x/Kconfig"
#New platform adds here
endmenu
+choice
+ prompt "ARC Instruction Set"
+ default ISA_ARCOMPACT
+
+config ISA_ARCOMPACT
+ bool "ARCompact ISA"
+ help
+ The original ARC ISA of ARC600/700 cores
+
+### For bisectability, disable ARCv2 support until we have all the bits in place
+#config ISA_ARCV2
+# bool "ARC ISA v2"
+# help
+# ISA for the Next Generation ARC-HS cores
+
+endchoice
+
menu "ARC CPU Configuration"
choice
prompt "ARC Core"
- default ARC_CPU_770
+ default ARC_CPU_770 if ISA_ARCOMPACT
+ default ARC_CPU_HS if ISA_ARCV2
+
+if ISA_ARCOMPACT
config ARC_CPU_750D
bool "ARC750D"
config ARC_CPU_770
bool "ARC770"
- select ARC_CPU_REL_4_10
+ select ARC_HAS_SWAPE
help
Support for ARC770 core introduced with Rel 4.10 (Summer 2011)
This core has a bunch of cool new features:
-Caches: New Prog Model, Region Flush
-Insns: endian swap, load-locked/store-conditional, time-stamp-ctr
+endif #ISA_ARCOMPACT
+
+config ARC_CPU_HS
+ bool "ARC-HS"
+ depends on ISA_ARCV2
+ help
+ Support for ARC HS38x Cores based on ARCv2 ISA
+ The notable features are:
+ - SMP configurations of upto 4 core with coherency
+ - Optional L2 Cache and IO-Coherency
+ - Revised Interrupt Architecture (multiple priorites, reg banks,
+ auto stack switch, auto regfile save/restore)
+ - MMUv4 (PIPT dcache, Huge Pages)
+ - Instructions for
+ * 64bit load/store: LDD, STD
+ * Hardware assisted divide/remainder: DIV, REM
+ * Function prologue/epilogue: ENTER_S, LEAVE_S
+ * IRQ enable/disable: CLRI, SETI
+ * pop count: FFS, FLS
+ * SETcc, BMSKN, XBFU...
+
endchoice
config CPU_BIG_ENDIAN
help
Build kernel for Big Endian Mode of ARC CPU
-# If a platform can't work with 0x8000_0000 based dma_addr_t
-config ARC_PLAT_NEEDS_CPU_TO_DMA
- bool
-
config SMP
bool "Symmetric Multi-Processing (Incomplete)"
default n
config ARC_HAS_REENTRANT_IRQ_LV2
def_bool n
-endif
+endif #SMP
config NR_CPUS
int "Maximum number of CPUs (2-4096)"
Multipler. Otherwise software multipy lib is used
choice
- prompt "ARC700 MMU Version"
+ prompt "MMU Version"
default ARC_MMU_V3 if ARC_CPU_770
default ARC_MMU_V2 if ARC_CPU_750D
endchoice
+if ISA_ARCOMPACT
+
config ARC_COMPACT_IRQ_LEVELS
bool "ARCompact IRQ Priorities: High(2)/Low(1)"
default n
config ARC_IRQ6_LV2
bool
-endif
+endif #ARC_COMPACT_IRQ_LEVELS
config ARC_FPU_SAVE_RESTORE
bool "Enable FPU state persistence across context switch"
based on actual usage of FPU by a task. Thus our implemn does
this for all tasks in system.
+endif #ISA_ARCOMPACT
+
config ARC_CANT_LLSC
def_bool n
-menuconfig ARC_CPU_REL_4_10
- bool "Enable support for Rel 4.10 features"
- default n
- help
- -ARC770 (and dependent features) enabled
- -ARC750 also shares some of the new features with 770
-
config ARC_HAS_LLSC
bool "Insn: LLOCK/SCOND (efficient atomic ops)"
default y
- depends on ARC_CPU_770 && !ARC_CANT_LLSC
+ depends on !ARC_CPU_750D && !ARC_CANT_LLSC
config ARC_HAS_SWAPE
bool "Insn: SWAPE (endian-swap)"
default y
- depends on ARC_CPU_REL_4_10
-config ARC_HAS_RTSC
- bool "Insn: RTSC (64-bit r/o cycle counter)"
+if ISA_ARCV2
+
+config ARC_HAS_LL64
+ bool "Insn: 64bit LDD/STD"
+ help
+ Enable gcc to generate 64-bit load/store instructions
+ ISA mandates even/odd registers to allow encoding of two
+ dest operands with 2 possible source operands.
default y
- depends on ARC_CPU_REL_4_10
- depends on !SMP
+
+config ARC_NUMBER_OF_INTERRUPTS
+ int "Number of interrupts"
+ range 8 240
+ default 32
+ help
+ This defines the number of interrupts on the ARCv2HS core.
+ It affects the size of vector table.
+ The initial 8 IRQs are fixed (Timer, ICI etc) and although configurable
+ in hardware, it keep things simple for Linux to assume they are always
+ present.
+
+endif # ISA_ARCV2
endmenu # "ARC CPU Configuration"
config ARC_EMUL_UNALIGNED
bool "Emulate unaligned memory access (userspace only)"
+ default N
select SYSCTL_ARCH_UNALIGN_NO_WARN
select SYSCTL_ARCH_UNALIGN_ALLOW
+ depends on ISA_ARCOMPACT
help
This enables misaligned 16 & 32 bit memory access from user space.
Use ONLY-IF-ABS-NECESSARY as it will be very slow and also can hide
Counts number of I and D TLB Misses and exports them via Debugfs
The counters can be cleared via Debugfs as well
+config ARC_UBOOT_SUPPORT
+ bool "Support uboot arg Handling"
+ default n
+ help
+ ARC Linux by default checks for uboot provided args as pointers to
+ external cmdline or DTB. This however breaks in absence of uboot,
+ when booting from Metaware debugger directly, as the registers are
+ not zeroed out on reset by mdb and/or ARCv2 based cores. The bogus
+ registers look like uboot args to kernel which then chokes.
+ So only enable the uboot arg checking/processing if users are sure
+ of uboot being in play.
+
config ARC_BUILTIN_DTB_NAME
string "Built in DTB"
help
projects / deliverable / linux.git / blobdiff