ARCv2: Support for ARCv2 ISA and HS38x cores

[deliverable/linux.git] / arch / arc / include / asm / ptrace.h

diff --git a/arch/arc/include/asm/ptrace.h b/arch/arc/include/asm/ptrace.h
index 1bfeec2c0558c2f6f91142105bee0c6ff70c7a75..91755972b9a25222c37a36e6b76dfd758cdbe771 100644 (file)
--- a/arch/arc/include/asm/ptrace.h
+++ b/arch/arc/include/asm/ptrace.h
@@ -16,6 +16,7 @@
 
 /* THE pt_regs: Defines how regs are saved during entry into kernel */
 
+#ifdef CONFIG_ISA_ARCOMPACT
 struct pt_regs {
 
        /* Real registers */
@@ -56,6 +57,48 @@ struct pt_regs {
 
        long user_r25;
 };
+#else
+
+struct pt_regs {
+
+       long orig_r0;
+
+       union {
+               struct {
+#ifdef CONFIG_CPU_BIG_ENDIAN
+                       unsigned long state:8, ecr_vec:8,
+                                     ecr_cause:8, ecr_param:8;
+#else
+                       unsigned long ecr_param:8, ecr_cause:8,
+                                     ecr_vec:8, state:8;
+#endif
+               };
+               unsigned long event;
+       };
+
+       long bta;       /* bta_l1, bta_l2, erbta */
+
+       long user_r25;
+
+       long r26;       /* gp */
+       long fp;
+       long sp;        /* user/kernel sp depending on where we came from  */
+
+       long r12;
+
+       /*------- Below list auto saved by h/w -----------*/
+       long r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, r10, r11;
+
+       long blink;
+       long lp_end, lp_start, lp_count;
+
+       long ei, ldi, jli;
+
+       long ret;
+       long status32;
+};
+
+#endif
 
 /* Callee saved registers - need to be saved only when you are scheduled out */