select HAVE_IDE
select RTC_LIB
select SYS_SUPPORTS_APM_EMULATION
+ select GENERIC_ATOMIC64 if (!CPU_32v6K)
select HAVE_OPROFILE
select HAVE_ARCH_KGDB
select HAVE_KPROBES if (!XIP_KERNEL)
select HAVE_GENERIC_DMA_COHERENT
select HAVE_KERNEL_GZIP
select HAVE_KERNEL_LZO
+ select HAVE_PERF_EVENTS
+ select PERF_USE_VMALLOC
help
The ARM series is a line of low-power-consumption RISC chip designs
licensed by ARM Ltd and targeted at embedded applications and
bool
select GENERIC_ALLOCATOR
+config HAVE_PROC_CPU
+ bool
+
config NO_IOPORT
bool
config ZONE_DMA
bool
+config NEED_DMA_MAP_STATE
+ def_bool y
+
config GENERIC_ISA_DMA
bool
config GENERIC_HARDIRQS_NO__DO_IRQ
def_bool y
+config ARM_L1_CACHE_SHIFT_6
+ bool
+ help
+ Setting ARM L1 cache line size to 64 Bytes.
+
if OPROFILE
config OPROFILE_ARMV6
Select if you want MMU-based virtualised addressing space
support by paged memory management. If unsure, say 'Y'.
+#
+# The "ARM system type" choice list is ordered alphabetically by option
+# text. Please add new entries in the option alphabetic order.
+#
choice
prompt "ARM system type"
default ARCH_VERSATILE
This enables support for systems based on the Atmel AT91RM9200,
AT91SAM9 and AT91CAP9 processors.
+config ARCH_BCMRING
+ bool "Broadcom BCMRING"
+ depends on MMU
+ select CPU_V6
+ select ARM_AMBA
+ select COMMON_CLKDEV
+ select GENERIC_TIME
+ select GENERIC_CLOCKEVENTS
+ select ARCH_WANT_OPTIONAL_GPIOLIB
+ help
+ Support for Broadcom's BCMRing platform.
+
config ARCH_CLPS711X
bool "Cirrus Logic CLPS711x/EP721x-based"
select CPU_ARM720T
help
This enables support for systems based on the Hynix HMS720x
-config ARCH_NOMADIK
- bool "STMicroelectronics Nomadik"
- select ARM_AMBA
- select ARM_VIC
- select CPU_ARM926T
- select HAVE_CLK
- select COMMON_CLKDEV
- select GENERIC_TIME
- select GENERIC_CLOCKEVENTS
- select GENERIC_GPIO
- select ARCH_REQUIRE_GPIOLIB
- help
- Support for the Nomadik platform by ST-Ericsson
-
config ARCH_IOP13XX
bool "IOP13xx-based"
depends on MMU
<http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
+config ARCH_NUC93X
+ bool "Nuvoton NUC93X CPU"
+ select CPU_ARM926T
+ select HAVE_CLK
+ select COMMON_CLKDEV
+ help
+ Support for Nuvoton (Winbond logic dept.) NUC93X MCU,The NUC93X is a
+ low-power and high performance MPEG-4/JPEG multimedia controller chip.
+
config ARCH_PNX4008
bool "Philips Nexperia PNX4008 Mobile"
select CPU_ARM926T
select HAVE_CLK
+ select COMMON_CLKDEV
help
This enables support for Philips PNX4008 mobile platform.
select GENERIC_GPIO
select HAVE_CLK
select CPU_V7
+ select ARM_L1_CACHE_SHIFT_6
help
Samsung S5PC1XX series based systems
help
Support for ST-Ericsson U300 series mobile platforms.
+config ARCH_U8500
+ bool "ST-Ericsson U8500 Series"
+ select CPU_V7
+ select ARM_AMBA
+ select GENERIC_TIME
+ select GENERIC_CLOCKEVENTS
+ select COMMON_CLKDEV
+ help
+ Support for ST-Ericsson's Ux500 architecture
+
+config ARCH_NOMADIK
+ bool "STMicroelectronics Nomadik"
+ select ARM_AMBA
+ select ARM_VIC
+ select CPU_ARM926T
+ select HAVE_CLK
+ select COMMON_CLKDEV
+ select GENERIC_TIME
+ select GENERIC_CLOCKEVENTS
+ select GENERIC_GPIO
+ select ARCH_REQUIRE_GPIOLIB
+ help
+ Support for the Nomadik platform by ST-Ericsson
+
config ARCH_DAVINCI
bool "TI DaVinci"
select CPU_ARM926T
help
Support for TI's OMAP platform (OMAP1 and OMAP2).
-config ARCH_BCMRING
- bool "Broadcom BCMRING"
- depends on MMU
- select CPU_V6
+config PLAT_SPEAR
+ bool "ST SPEAr"
select ARM_AMBA
+ select ARCH_REQUIRE_GPIOLIB
select COMMON_CLKDEV
- select GENERIC_TIME
select GENERIC_CLOCKEVENTS
- select ARCH_WANT_OPTIONAL_GPIOLIB
- help
- Support for Broadcom's BCMRing platform.
-
-config ARCH_U8500
- bool "ST-Ericsson U8500 Series"
- select CPU_V7
- select ARM_AMBA
+ select GENERIC_GPIO
select GENERIC_TIME
- select GENERIC_CLOCKEVENTS
- select COMMON_CLKDEV
+ select HAVE_CLK
help
- Support for ST-Ericsson's Ux500 architecture
+ Support for ST's SPEAr platform (SPEAr3xx, SPEAr6xx and SPEAr13xx).
endchoice
+#
+# This is sorted alphabetically by mach-* pathname. However, plat-*
+# Kconfigs may be included either alphabetically (according to the
+# plat- suffix) or along side the corresponding mach-* source.
+#
source "arch/arm/mach-aaec2000/Kconfig"
source "arch/arm/mach-at91/Kconfig"
source "arch/arm/mach-ns9xxx/Kconfig"
+source "arch/arm/mach-nuc93x/Kconfig"
+
source "arch/arm/plat-omap/Kconfig"
source "arch/arm/mach-omap1/Kconfig"
source "arch/arm/plat-s3c24xx/Kconfig"
source "arch/arm/plat-s5p/Kconfig"
source "arch/arm/plat-s5pc1xx/Kconfig"
+source "arch/arm/plat-spear/Kconfig"
if ARCH_S3C2410
source "arch/arm/mach-s3c2400/Kconfig"
depends on CPU_XSCALE && !XSCALE_PMU_TIMER
default y
+config CPU_HAS_PMU
+ depends on CPU_V6 || CPU_V7 || XSCALE_PMU
+ default y
+ bool
+
if !MMU
source "arch/arm/Kconfig-nommu"
endif
ACTLR register. Note that setting specific bits in the ACTLR register
may not be available in non-secure mode.
+config PL310_ERRATA_588369
+ bool "Clean & Invalidate maintenance operations do not invalidate clean lines"
+ depends on CACHE_L2X0 && ARCH_OMAP4
+ help
+ The PL310 L2 cache controller implements three types of Clean &
+ Invalidate maintenance operations: by Physical Address
+ (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
+ They are architecturally defined to behave as the execution of a
+ clean operation followed immediately by an invalidate operation,
+ both performing to the same memory location. This functionality
+ is not correctly implemented in PL310 as clean lines are not
+ invalidated as a result of these operations. Note that this errata
+ uses Texas Instrument's secure monitor api.
endmenu
source "arch/arm/common/Kconfig"
depends on HIGHMEM
depends on !OUTER_CACHE
+config HW_PERF_EVENTS
+ bool "Enable hardware performance counter support for perf events"
+ depends on PERF_EVENTS && CPU_HAS_PMU && (CPU_V6 || CPU_V7)
+ default y
+ help
+ Enable hardware performance counter support for perf events. If
+ disabled, perf events will use software events only.
+
source "mm/Kconfig"
config LEDS
bool
depends on CPU_CP15_MMU
default y if !ARCH_EBSA110
+ select HAVE_PROC_CPU if PROC_FS
help
ARM processors cannot fetch/store information which is not
naturally aligned on the bus, i.e., a 4 byte fetch must start at an