pmu_system_controller: system-controller@10020000 {
compatible = "samsung,exynos3250-pmu", "syscon";
reg = <0x10020000 0x4000>;
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ interrupt-parent = <&gic>;
};
mipi_phy: video-phy@10020710 {
compatible = "samsung,exynos3250-cmu";
reg = <0x10030000 0x20000>;
#clock-cells = <1>;
+ assigned-clocks = <&cmu CLK_MOUT_ACLK_400_MCUISP_SUB>,
+ <&cmu CLK_MOUT_ACLK_266_SUB>;
+ assigned-clock-parents = <&cmu CLK_FIN_PLL>,
+ <&cmu CLK_FIN_PLL>;
};
cmu_dmc: clock-controller@105C0000 {
};
rtc: rtc@10070000 {
- compatible = "samsung,exynos3250-rtc";
+ compatible = "samsung,s3c6410-rtc";
reg = <0x10070000 0x100>;
interrupts = <0 73 0>, <0 74 0>;
+ interrupt-parent = <&pmu_system_controller>;
status = "disabled";
};
interrupts = <0 240 0>;
};
+ jpeg: codec@11830000 {
+ compatible = "samsung,exynos3250-jpeg";
+ reg = <0x11830000 0x1000>;
+ interrupts = <0 171 0>;
+ clocks = <&cmu CLK_JPEG>, <&cmu CLK_SCLK_JPEG>;
+ clock-names = "jpeg", "sclk";
+ power-domains = <&pd_cam>;
+ assigned-clocks = <&cmu CLK_MOUT_CAM_BLK>, <&cmu CLK_SCLK_JPEG>;
+ assigned-clock-rates = <0>, <150000000>;
+ assigned-clock-parents = <&cmu CLK_DIV_MPLL_PRE>;
+ iommus = <&sysmmu_jpeg>;
+ status = "disabled";
+ };
+
+ sysmmu_jpeg: sysmmu@11A60000 {
+ compatible = "samsung,exynos-sysmmu";
+ reg = <0x11a60000 0x1000>;
+ interrupts = <0 156 0>, <0 161 0>;
+ clock-names = "sysmmu", "master";
+ clocks = <&cmu CLK_SMMUJPEG>, <&cmu CLK_JPEG>;
+ power-domains = <&pd_cam>;
+ #iommu-cells = <0>;
+ };
+
fimd: fimd@11c00000 {
compatible = "samsung,exynos3250-fimd";
reg = <0x11c00000 0x30000>;
clocks = <&cmu CLK_SCLK_FIMD0>, <&cmu CLK_FIMD0>;
clock-names = "sclk_fimd", "fimd";
power-domains = <&pd_lcd0>;
+ iommus = <&sysmmu_fimd0>;
samsung,sysreg = <&sys_reg>;
status = "disabled";
};
status = "disabled";
};
+ sysmmu_fimd0: sysmmu@11E20000 {
+ compatible = "samsung,exynos-sysmmu";
+ reg = <0x11e20000 0x1000>;
+ interrupts = <0 80 0>, <0 81 0>;
+ clock-names = "sysmmu", "master";
+ clocks = <&cmu CLK_SMMUFIMD0>, <&cmu CLK_FIMD0>;
+ power-domains = <&pd_lcd0>;
+ #iommu-cells = <0>;
+ };
+
hsotg: hsotg@12480000 {
compatible = "snps,dwc2";
reg = <0x12480000 0x20000>;
clock-names = "mfc", "sclk_mfc";
clocks = <&cmu CLK_MFC>, <&cmu CLK_SCLK_MFC>;
power-domains = <&pd_mfc>;
+ iommus = <&sysmmu_mfc>;
status = "disabled";
};
+ sysmmu_mfc: sysmmu@13620000 {
+ compatible = "samsung,exynos-sysmmu";
+ reg = <0x13620000 0x1000>;
+ interrupts = <0 96 0>, <0 98 0>;
+ clock-names = "sysmmu", "master";
+ clocks = <&cmu CLK_SMMUMFC_L>, <&cmu CLK_MFC>;
+ power-domains = <&pd_mfc>;
+ #iommu-cells = <0>;
+ };
+
serial_0: serial@13800000 {
compatible = "samsung,exynos4210-uart";
reg = <0x13800000 0x100>;