ARM: dts: imx: add initial imx6dl-sabresd support

[deliverable/linux.git] / arch / arm / boot / dts / imx6dl.dtsi

diff --git a/arch/arm/boot/dts/imx6dl.dtsi b/arch/arm/boot/dts/imx6dl.dtsi
index 63fafe2a606cd4502b17f6a1b762ef1633436b53..3e07f6e9095c68b400b87a9a969bb07d9d658211 100644 (file)
--- a/arch/arm/boot/dts/imx6dl.dtsi
+++ b/arch/arm/boot/dts/imx6dl.dtsi
@@ -1,3 +1,4 @@
+
 /*
  * Copyright 2013 Freescale Semiconductor, Inc.
  *
@@ -7,7 +8,8 @@
  *
  */
 
-/include/ "imx6qdl.dtsi"
+#include "imx6qdl.dtsi"
+#include "imx6dl-pinfunc.h"
 
 / {
        cpus {
@@ -29,6 +31,87 @@
 
        soc {
                aips1: aips-bus@02000000 {
+                       iomuxc: iomuxc@020e0000 {
+                               compatible = "fsl,imx6dl-iomuxc";
+                               reg = <0x020e0000 0x4000>;
+
+                               enet {
+                                       pinctrl_enet_1: enetgrp-1 {
+                                               fsl,pins = <
+                                                       MX6DL_PAD_ENET_MDIO__ENET_MDIO       0x1b0b0
+                                                       MX6DL_PAD_ENET_MDC__ENET_MDC         0x1b0b0
+                                                       MX6DL_PAD_RGMII_TXC__RGMII_TXC       0x1b0b0
+                                                       MX6DL_PAD_RGMII_TD0__RGMII_TD0       0x1b0b0
+                                                       MX6DL_PAD_RGMII_TD1__RGMII_TD1       0x1b0b0
+                                                       MX6DL_PAD_RGMII_TD2__RGMII_TD2       0x1b0b0
+                                                       MX6DL_PAD_RGMII_TD3__RGMII_TD3       0x1b0b0
+                                                       MX6DL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
+                                                       MX6DL_PAD_ENET_REF_CLK__ENET_TX_CLK  0x1b0b0
+                                                       MX6DL_PAD_RGMII_RXC__RGMII_RXC       0x1b0b0
+                                                       MX6DL_PAD_RGMII_RD0__RGMII_RD0       0x1b0b0
+                                                       MX6DL_PAD_RGMII_RD1__RGMII_RD1       0x1b0b0
+                                                       MX6DL_PAD_RGMII_RD2__RGMII_RD2       0x1b0b0
+                                                       MX6DL_PAD_RGMII_RD3__RGMII_RD3       0x1b0b0
+                                                       MX6DL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
+                                                       MX6DL_PAD_GPIO_16__ENET_REF_CLK      0x4001b0a8
+                                               >;
+                                       };
+                               };
+
+                               uart1 {
+                                       pinctrl_uart1_1: uart1grp-1 {
+                                               fsl,pins = <
+                                                       MX6DL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
+                                                       MX6DL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
+                                               >;
+                                       };
+                               };
+
+                               usbotg {
+                                       pinctrl_usbotg_2: usbotggrp-2 {
+                                               fsl,pins = <
+                                                       MX6DL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059
+                                               >;
+                                       };
+                               };
+
+                               usdhc2 {
+                                       pinctrl_usdhc2_1: usdhc2grp-1 {
+                                               fsl,pins = <
+                                                       MX6DL_PAD_SD2_CMD__SD2_CMD    0x17059
+                                                       MX6DL_PAD_SD2_CLK__SD2_CLK    0x10059
+                                                       MX6DL_PAD_SD2_DAT0__SD2_DATA0 0x17059
+                                                       MX6DL_PAD_SD2_DAT1__SD2_DATA1 0x17059
+                                                       MX6DL_PAD_SD2_DAT2__SD2_DATA2 0x17059
+                                                       MX6DL_PAD_SD2_DAT3__SD2_DATA3 0x17059
+                                                       MX6DL_PAD_NANDF_D4__SD2_DATA4 0x17059
+                                                       MX6DL_PAD_NANDF_D5__SD2_DATA5 0x17059
+                                                       MX6DL_PAD_NANDF_D6__SD2_DATA6 0x17059
+                                                       MX6DL_PAD_NANDF_D7__SD2_DATA7 0x17059
+                                               >;
+                                       };
+                               };
+
+                               usdhc3 {
+                                       pinctrl_usdhc3_1: usdhc3grp-1 {
+                                               fsl,pins = <
+                                                       MX6DL_PAD_SD3_CMD__SD3_CMD    0x17059
+                                                       MX6DL_PAD_SD3_CLK__SD3_CLK    0x10059
+                                                       MX6DL_PAD_SD3_DAT0__SD3_DATA0 0x17059
+                                                       MX6DL_PAD_SD3_DAT1__SD3_DATA1 0x17059
+                                                       MX6DL_PAD_SD3_DAT2__SD3_DATA2 0x17059
+                                                       MX6DL_PAD_SD3_DAT3__SD3_DATA3 0x17059
+                                                       MX6DL_PAD_SD3_DAT4__SD3_DATA4 0x17059
+                                                       MX6DL_PAD_SD3_DAT5__SD3_DATA5 0x17059
+                                                       MX6DL_PAD_SD3_DAT6__SD3_DATA6 0x17059
+                                                       MX6DL_PAD_SD3_DAT7__SD3_DATA7 0x17059
+                                               >;
+                                       };
+                               };
+
+
+                       };
+
                        pxp: pxp@020f0000 {
                                reg = <0x020f0000 0x4000>;
                                interrupts = <0 98 0x04>;