clock-latency = <61036>; /* two CLK32 periods */
operating-points = <
/* kHz uV */
- 528000 1250000
- 396000 1150000
- 198000 1150000
+ 528000 1175000
+ 396000 1025000
+ 198000 950000
>;
fsl,soc-operating-points = <
/* KHz uV */
- 528000 1250000
- 396000 1150000
- 198000 1150000
+ 528000 1175000
+ 396000 1175000
+ 198000 1175000
>;
clocks = <&clks IMX6UL_CLK_ARM>,
<&clks IMX6UL_CLK_PLL2_BUS>,