ARM: dts: STi: STih407: Switch LPC mode from RTC to Clocksource

[deliverable/linux.git] / arch / arm / boot / dts / qcom-msm8974.dtsi

diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom-msm8974.dtsi
index dfdafdcb8aae99711507bc4abfbbd7374ba39205..ef53305784318a40d692fa7053a631abac28e552 100644 (file)
--- a/arch/arm/boot/dts/qcom-msm8974.dtsi
+++ b/arch/arm/boot/dts/qcom-msm8974.dtsi
@@ -1,6 +1,6 @@
 /dts-v1/;
 
-#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/clock/qcom,gcc-msm8974.h>
 #include "skeleton.dtsi"
 
@@ -14,10 +14,50 @@
                #size-cells = <1>;
                ranges;
 
+               mpss@08000000 {
+                       reg = <0x08000000 0x5100000>;
+                       no-map;
+               };
+
+               mba@00d100000 {
+                       reg = <0x0d100000 0x100000>;
+                       no-map;
+               };
+
+               reserved@0d200000 {
+                       reg = <0x0d200000 0xa00000>;
+                       no-map;
+               };
+
+               adsp@0dc00000 {
+                       reg = <0x0dc00000 0x1900000>;
+                       no-map;
+               };
+
+               venus@0f500000 {
+                       reg = <0x0f500000 0x500000>;
+                       no-map;
+               };
+
                smem_region: smem@fa00000 {
                        reg = <0xfa00000 0x200000>;
                        no-map;
                };
+
+               tz@0fc00000 {
+                       reg = <0x0fc00000 0x160000>;
+                       no-map;
+               };
+
+               efs@0fd600000 {
+                       reg = <0x0fd60000 0x1a0000>;
+                       no-map;
+               };
+
+               unused@0ff00000 {
+                       reg = <0x0ff00000 0x10100000>;
+                       no-map;
+               };
        };
 
        cpus {
@@ -91,6 +131,20 @@
                interrupts = <1 7 0xf04>;
        };
 
+       clocks {
+               xo_board {
+                       compatible = "fixed-clock";
+                       #clock-cells = <0>;
+                       clock-frequency = <19200000>;
+               };
+
+               sleep_clk {
+                       compatible = "fixed-clock";
+                       #clock-cells = <0>;
+                       clock-frequency = <32768>;
+               };
+       };
+
        timer {
                compatible = "arm,armv7-timer";
                interrupts = <1 2 0xf08>,
@@ -109,6 +163,73 @@
                hwlocks = <&tcsr_mutex 3>;
        };
 
+       smp2p-wcnss {
+               compatible = "qcom,smp2p";
+               qcom,smem = <451>, <431>;
+
+               interrupt-parent = <&intc>;
+               interrupts = <0 143 IRQ_TYPE_EDGE_RISING>;
+
+               qcom,ipc = <&apcs 8 18>;
+
+               qcom,local-pid = <0>;
+               qcom,remote-pid = <4>;
+
+               wcnss_smp2p_out: master-kernel {
+                       qcom,entry-name = "master-kernel";
+
+                       #qcom,state-cells = <1>;
+               };
+
+               wcnss_smp2p_in: slave-kernel {
+                       qcom,entry-name = "slave-kernel";
+
+                       interrupt-controller;
+                       #interrupt-cells = <2>;
+               };
+       };
+
+       smsm {
+               compatible = "qcom,smsm";
+
+               #address-cells = <1>;
+               #size-cells = <0>;
+
+               qcom,ipc-1 = <&apcs 8 13>;
+               qcom,ipc-2 = <&apcs 8 9>;
+               qcom,ipc-3 = <&apcs 8 19>;
+
+               apps_smsm: apps@0 {
+                       reg = <0>;
+
+                       #qcom,state-cells = <1>;
+               };
+
+               modem_smsm: modem@1 {
+                       reg = <1>;
+                       interrupts = <0 26 IRQ_TYPE_EDGE_RISING>;
+
+                       interrupt-controller;
+                       #interrupt-cells = <2>;
+               };
+
+               adsp_smsm: adsp@2 {
+                       reg = <2>;
+                       interrupts = <0 157 IRQ_TYPE_EDGE_RISING>;
+
+                       interrupt-controller;
+                       #interrupt-cells = <2>;
+               };
+
+               wcnss_smsm: wcnss@7 {
+                       reg = <7>;
+                       interrupts = <0 144 IRQ_TYPE_EDGE_RISING>;
+
+                       interrupt-controller;
+                       #interrupt-cells = <2>;
+               };
+       };
+
        soc: soc {
                #address-cells = <1>;
                #size-cells = <1>;
@@ -339,6 +460,8 @@
                        clock-names = "core", "iface";
                        #address-cells = <1>;
                        #size-cells = <0>;
+                       dmas = <&blsp2_dma 20>, <&blsp2_dma 21>;
+                       dma-names = "tx", "rx";
                };
 
                spmi_bus: spmi@fc4cf000 {
@@ -356,6 +479,16 @@
                        interrupt-controller;
                        #interrupt-cells = <4>;
                };
+
+               blsp2_dma: dma-controller@f9944000 {
+                       compatible = "qcom,bam-v1.4.0";
+                       reg = <0xf9944000 0x19000>;
+                       interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&gcc GCC_BLSP2_AHB_CLK>;
+                       clock-names = "bam_clk";
+                       #dma-cells = <1>;
+                       qcom,ee = <0>;
+               };
        };
 
        smd {