Merge tag 'zynq-dt-for-3.19' of https://github.com/Xilinx/linux-xlnx into next/dt

[deliverable/linux.git] / arch / arm / boot / dts / zynq-7000.dtsi

diff --git a/arch/arm/boot/dts/zynq-7000.dtsi b/arch/arm/boot/dts/zynq-7000.dtsi
index 772381fe07bb0fd550571c1940ffc5f4cfb882da..ee3e5d675b053fca340ec8a3ca98c0cc012f044c 100644 (file)
--- a/arch/arm/boot/dts/zynq-7000.dtsi
+++ b/arch/arm/boot/dts/zynq-7000.dtsi
@@ -64,7 +64,7 @@
                interrupt-parent = <&intc>;
                ranges;
 
-               adc@f8007100 {
+               adc: adc@f8007100 {
                        compatible = "xlnx,zynq-xadc-1.00.a";
                        reg = <0xf8007100 0x20>;
                        interrupts = <0 7 4>;
@@ -145,10 +145,10 @@
                        cache-level = <2>;
                };
 
-               memory-controller@f8006000 {
+               mc: memory-controller@f8006000 {
                        compatible = "xlnx,zynq-ddrc-a05";
                        reg = <0xf8006000 0x1000>;
-               } ;
+               };
 
                uart0: serial@e0000000 {
                        compatible = "xlnx,xuartps", "cdns,uart-r1p8";
@@ -243,7 +243,6 @@
                        clkc: clkc@100 {
                                #clock-cells = <1>;
                                compatible = "xlnx,ps7-clkc";
-                               ps-clk-frequency = <33333333>;
                                fclk-enable = <0>;
                                clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x",
                                                "cpu_3or2x", "cpu_2x", "cpu_1x", "ddr2x", "ddr3x",
@@ -314,5 +313,16 @@
                        reg = <0xf8f00600 0x20>;
                        clocks = <&clkc 4>;
                };
+
+               watchdog0: watchdog@f8005000 {
+                       clocks = <&clkc 45>;
+                       compatible = "xlnx,zynq-wdt-r1p2";
+                       device_type = "watchdog";
+                       interrupt-parent = <&intc>;
+                       interrupts = <0 9 1>;
+                       reg = <0xf8005000 0x1000>;
+                       reset = <0>;
+                       timeout-sec = <10>;
+               };
        };
 };