ARM: 5580/2: ARM TCM (Tightly-Coupled Memory) support v3

[deliverable/linux.git] / arch / arm / include / asm / cputype.h

diff --git a/arch/arm/include/asm/cputype.h b/arch/arm/include/asm/cputype.h
index 7b9d27e749b8e8afefbff6a292bbb334adcac636..54a1f1d76b14516901380a13cdfc0801bc373630 100644 (file)
--- a/arch/arm/include/asm/cputype.h
+++ b/arch/arm/include/asm/cputype.h
@@ -8,6 +8,21 @@
 #define CPUID_TCM      2
 #define CPUID_TLBTYPE  3
 
+#define CPUID_EXT_PFR0 "c1, 0"
+#define CPUID_EXT_PFR1 "c1, 1"
+#define CPUID_EXT_DFR0 "c1, 2"
+#define CPUID_EXT_AFR0 "c1, 3"
+#define CPUID_EXT_MMFR0        "c1, 4"
+#define CPUID_EXT_MMFR1        "c1, 5"
+#define CPUID_EXT_MMFR2        "c1, 6"
+#define CPUID_EXT_MMFR3        "c1, 7"
+#define CPUID_EXT_ISAR0        "c2, 0"
+#define CPUID_EXT_ISAR1        "c2, 1"
+#define CPUID_EXT_ISAR2        "c2, 2"
+#define CPUID_EXT_ISAR3        "c2, 3"
+#define CPUID_EXT_ISAR4        "c2, 4"
+#define CPUID_EXT_ISAR5        "c2, 5"
+
 #ifdef CONFIG_CPU_CP15
 #define read_cpuid(reg)                                                        \
        ({                                                              \
@@ -18,9 +33,19 @@
                    : "cc");                                            \
                __val;                                                  \
        })
+#define read_cpuid_ext(ext_reg)                                                \
+       ({                                                              \
+               unsigned int __val;                                     \
+               asm("mrc        p15, 0, %0, c0, " ext_reg               \
+                   : "=r" (__val)                                      \
+                   :                                                   \
+                   : "cc");                                            \
+               __val;                                                  \
+       })
 #else
 extern unsigned int processor_id;
 #define read_cpuid(reg) (processor_id)
+#define read_cpuid_ext(reg) 0
 #endif
 
 /*
@@ -38,6 +63,11 @@ static inline unsigned int __attribute_const__ read_cpuid_cachetype(void)
        return read_cpuid(CPUID_CACHETYPE);
 }
 
+static inline unsigned int __attribute_const__ read_cpuid_tcmstatus(void)
+{
+       return read_cpuid(CPUID_TCM);
+}
+
 /*
  * Intel's XScale3 core supports some v6 features (supersections, L2)
  * but advertises itself as v5 as it does not support the v6 ISA.  For