Merge branch 'next/fixes-non-critical' into next/cleanup

[deliverable/linux.git] / arch / arm / mach-exynos / platsmp.c

diff --git a/arch/arm/mach-exynos/platsmp.c b/arch/arm/mach-exynos/platsmp.c
index ec02422e84993d4bb8f813e5976ffd9fe3b3bdeb..51e941aed8b9b7bdbff30d54c7ff6338ef7f3d9d 100644 (file)
--- a/arch/arm/mach-exynos/platsmp.c
+++ b/arch/arm/mach-exynos/platsmp.c
@@ -1,5 +1,4 @@
-/* linux/arch/arm/mach-exynos4/platsmp.c
- *
+ /*
  * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
  *             http://www.samsung.com
  *
@@ -32,26 +31,70 @@
 
 extern void exynos4_secondary_startup(void);
 
-void __iomem *sysram_base_addr;
-void __iomem *sysram_ns_base_addr;
+/**
+ * exynos_core_power_down : power down the specified cpu
+ * @cpu : the cpu to power down
+ *
+ * Power down the specified cpu. The sequence must be finished by a
+ * call to cpu_do_idle()
+ *
+ */
+void exynos_cpu_power_down(int cpu)
+{
+       __raw_writel(0, EXYNOS_ARM_CORE_CONFIGURATION(cpu));
+}
 
-static void __init exynos_smp_prepare_sysram(void)
+/**
+ * exynos_cpu_power_up : power up the specified cpu
+ * @cpu : the cpu to power up
+ *
+ * Power up the specified cpu
+ */
+void exynos_cpu_power_up(int cpu)
 {
-       struct device_node *node;
+       __raw_writel(S5P_CORE_LOCAL_PWR_EN,
+                    EXYNOS_ARM_CORE_CONFIGURATION(cpu));
+}
 
-       for_each_compatible_node(node, NULL, "samsung,exynos4210-sysram") {
-               if (!of_device_is_available(node))
-                       continue;
-               sysram_base_addr = of_iomap(node, 0);
-               break;
-       }
+/**
+ * exynos_cpu_power_state : returns the power state of the cpu
+ * @cpu : the cpu to retrieve the power state from
+ *
+ */
+int exynos_cpu_power_state(int cpu)
+{
+       return (__raw_readl(EXYNOS_ARM_CORE_STATUS(cpu)) &
+                       S5P_CORE_LOCAL_PWR_EN);
+}
 
-       for_each_compatible_node(node, NULL, "samsung,exynos4210-sysram-ns") {
-               if (!of_device_is_available(node))
-                       continue;
-               sysram_ns_base_addr = of_iomap(node, 0);
-               break;
-       }
+/**
+ * exynos_cluster_power_down : power down the specified cluster
+ * @cluster : the cluster to power down
+ */
+void exynos_cluster_power_down(int cluster)
+{
+       __raw_writel(0, EXYNOS_COMMON_CONFIGURATION(cluster));
+}
+
+/**
+ * exynos_cluster_power_up : power up the specified cluster
+ * @cluster : the cluster to power up
+ */
+void exynos_cluster_power_up(int cluster)
+{
+       __raw_writel(S5P_CORE_LOCAL_PWR_EN,
+                    EXYNOS_COMMON_CONFIGURATION(cluster));
+}
+
+/**
+ * exynos_cluster_power_state : returns the power state of the cluster
+ * @cluster : the cluster to retrieve the power state from
+ *
+ */
+int exynos_cluster_power_state(int cluster)
+{
+       return (__raw_readl(EXYNOS_COMMON_STATUS(cluster)) &
+                       S5P_CORE_LOCAL_PWR_EN);
 }
 
 static inline void __iomem *cpu_boot_reg_base(void)
@@ -234,11 +277,11 @@ static void __init exynos_smp_prepare_cpus(unsigned int max_cpus)
 {
        int i;
 
+       exynos_sysram_init();
+
        if (read_cpuid_part_number() == ARM_CPU_PART_CORTEX_A9)
                scu_enable(scu_base_addr());
 
-       exynos_smp_prepare_sysram();
-
        /*
         * Write the address of secondary startup into the
         * system-wide flags register. The boot monitor waits