Merge branch 'i2c/for-next' of git://git.kernel.org/pub/scm/linux/kernel/git/wsa...

[deliverable/linux.git] / arch / arm / mach-imx / system.c

diff --git a/arch/arm/mach-imx/system.c b/arch/arm/mach-imx/system.c
index 51c35013b673b0d356c12ae8d0853557243c1f34..105d1ce4ed9d1400da09d476c03761e2de5c982e 100644 (file)
--- a/arch/arm/mach-imx/system.c
+++ b/arch/arm/mach-imx/system.c
@@ -54,7 +54,7 @@ void mxc_restart(enum reboot_mode mode, const char *cmd)
                wcr_enable = (1 << 2);
 
        /* Assert SRS signal */
-       __raw_writew(wcr_enable, wdog_base);
+       imx_writew(wcr_enable, wdog_base);
        /*
         * Due to imx6q errata ERR004346 (WDOG: WDOG SRS bit requires to be
         * written twice), we add another two writes to ensure there must be at
@@ -62,8 +62,8 @@ void mxc_restart(enum reboot_mode mode, const char *cmd)
         * the target check here, since the writes shouldn't be a huge burden
         * for other platforms.
         */
-       __raw_writew(wcr_enable, wdog_base);
-       __raw_writew(wcr_enable, wdog_base);
+       imx_writew(wcr_enable, wdog_base);
+       imx_writew(wcr_enable, wdog_base);
 
        /* wait for reset to assert... */
        mdelay(500);
@@ -106,6 +106,9 @@ void __init imx_init_l2cache(void)
                goto out;
        }
 
+       if (readl_relaxed(l2x0_base + L2X0_CTRL) & L2X0_CTRL_EN)
+               goto skip_if_enabled;
+
        /* Configure the L2 PREFETCH and POWER registers */
        val = readl_relaxed(l2x0_base + L310_PREFETCH_CTRL);
        val |= 0x70800000;
@@ -122,6 +125,7 @@ void __init imx_init_l2cache(void)
                val &= ~(1 << 30 | 1 << 23);
        writel_relaxed(val, l2x0_base + L310_PREFETCH_CTRL);
 
+skip_if_enabled:
        iounmap(l2x0_base);
        of_node_put(np);