arm: plat-orion: use void __iomem pointers for addr-map functions

[deliverable/linux.git] / arch / arm / mach-mv78xx0 / addr-map.c

diff --git a/arch/arm/mach-mv78xx0/addr-map.c b/arch/arm/mach-mv78xx0/addr-map.c
index 62b53d710efde1a0a71095b2e9e54186cb454886..a51fc247e73bb33f4486ec79d2b52233df2eb174 100644 (file)
--- a/arch/arm/mach-mv78xx0/addr-map.c
+++ b/arch/arm/mach-mv78xx0/addr-map.c
@@ -37,7 +37,7 @@
 #define WIN0_OFF(n)            (BRIDGE_VIRT_BASE + 0x0000 + ((n) << 4))
 #define WIN8_OFF(n)            (BRIDGE_VIRT_BASE + 0x0900 + (((n) - 8) << 4))
 
-static void __init __iomem *win_cfg_base(int win)
+static void __init __iomem *win_cfg_base(const struct orion_addr_map_cfg *cfg, int win)
 {
        /*
         * Find the control register base address for this window.
@@ -47,7 +47,7 @@ static void __init __iomem *win_cfg_base(int win)
         * so we don't need to take that into account here.
         */
 
-       return (void __iomem *)((win < 8) ? WIN0_OFF(win) : WIN8_OFF(win));
+       return (win < 8) ? WIN0_OFF(win) : WIN8_OFF(win);
 }
 
 /*
@@ -71,10 +71,10 @@ void __init mv78xx0_setup_cpu_mbus(void)
         */
        if (mv78xx0_core_index() == 0)
                orion_setup_cpu_mbus_target(&addr_map_cfg,
-                                           DDR_WINDOW_CPU0_BASE);
+                                           (void __iomem *) DDR_WINDOW_CPU0_BASE);
        else
                orion_setup_cpu_mbus_target(&addr_map_cfg,
-                                           DDR_WINDOW_CPU1_BASE);
+                                           (void __iomem *) DDR_WINDOW_CPU1_BASE);
 }
 
 void __init mv78xx0_setup_pcie_io_win(int window, u32 base, u32 size,