i.MX35: Add USB control register access support

[deliverable/linux.git] / arch / arm / plat-mxc / ehci.c

diff --git a/arch/arm/plat-mxc/ehci.c b/arch/arm/plat-mxc/ehci.c
index 816a9cc60e5d042e78fb39829b20de6a2be9f870..cb0b638744824344f26672b854b56e86ddf00e2d 100644 (file)
--- a/arch/arm/plat-mxc/ehci.c
+++ b/arch/arm/plat-mxc/ehci.c
@@ -38,6 +38,18 @@
 #define MX31_H1_PM_BIT         (1 << 8)
 #define MX31_H1_DT_BIT         (1 << 4)
 
+#define MX35_OTG_SIC_SHIFT     29
+#define MX35_OTG_SIC_MASK      (0x3 << MX35_OTG_SIC_SHIFT)
+#define MX35_OTG_PM_BIT                (1 << 24)
+
+#define MX35_H1_SIC_SHIFT      21
+#define MX35_H1_SIC_MASK       (0x3 << MX35_H1_SIC_SHIFT)
+#define MX35_H1_PM_BIT         (1 << 8)
+#define MX35_H1_IPPUE_UP_BIT   (1 << 7)
+#define MX35_H1_IPPUE_DOWN_BIT (1 << 6)
+#define MX35_H1_TLL_BIT                (1 << 5)
+#define MX35_H1_USBTE_BIT      (1 << 4)
+
 int mxc_set_usbcontrol(int port, unsigned int flags)
 {
        unsigned int v;
@@ -85,6 +97,49 @@ int mxc_set_usbcontrol(int port, unsigned int flags)
                                     USBCTRL_OTGBASE_OFFSET));
                return 0;
        }
+
+       if (cpu_is_mx35()) {
+               v = readl(MX35_IO_ADDRESS(MX35_OTG_BASE_ADDR +
+                                    USBCTRL_OTGBASE_OFFSET));
+
+               switch (port) {
+               case 0: /* OTG port */
+                       v &= ~(MX35_OTG_SIC_MASK | MX35_OTG_PM_BIT);
+                       v |= (flags & MXC_EHCI_INTERFACE_MASK)
+                                       << MX35_OTG_SIC_SHIFT;
+                       if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
+                               v |= MX35_OTG_PM_BIT;
+
+                       break;
+               case 1: /* H1 port */
+                       v &= ~(MX35_H1_SIC_MASK | MX35_H1_PM_BIT | MX35_H1_TLL_BIT |
+                               MX35_H1_USBTE_BIT | MX35_H1_IPPUE_DOWN_BIT | MX35_H1_IPPUE_UP_BIT);
+                       v |= (flags & MXC_EHCI_INTERFACE_MASK)
+                                               << MX35_H1_SIC_SHIFT;
+                       if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
+                               v |= MX35_H1_PM_BIT;
+
+                       if (!(flags & MXC_EHCI_TTL_ENABLED))
+                               v |= MX35_H1_TLL_BIT;
+
+                       if (flags & MXC_EHCI_INTERNAL_PHY)
+                               v |= MX35_H1_USBTE_BIT;
+
+                       if (flags & MXC_EHCI_IPPUE_DOWN)
+                               v |= MX35_H1_IPPUE_DOWN_BIT;
+
+                       if (flags & MXC_EHCI_IPPUE_UP)
+                               v |= MX35_H1_IPPUE_UP_BIT;
+
+                       break;
+               default:
+                       return -EINVAL;
+               }
+
+               writel(v, MX35_IO_ADDRESS(MX35_OTG_BASE_ADDR +
+                                    USBCTRL_OTGBASE_OFFSET));
+               return 0;
+       }
 #endif /* CONFIG_ARCH_MX3 */
 #ifdef CONFIG_MACH_MX27
        if (cpu_is_mx27()) {