Merge branch 'for_linus' of git://git.kernel.org/pub/scm/linux/kernel/git/jack/linux...

[deliverable/linux.git] / arch / m68k / include / asm / m5272sim.h

diff --git a/arch/m68k/include/asm/m5272sim.h b/arch/m68k/include/asm/m5272sim.h
index 6217edc2113955f7f6d722baf6d704ec562ed194..df3332c2317de8ae95eff60752596b5e0b962793 100644 (file)
--- a/arch/m68k/include/asm/m5272sim.h
+++ b/arch/m68k/include/asm/m5272sim.h
@@ -12,7 +12,6 @@
 #define        m5272sim_h
 /****************************************************************************/
 
-
 /*
  *     Define the 5272 SIM register set addresses.
  */
@@ -63,16 +62,59 @@
 #define        MCFSIM_DCMR1            0x5c            /* DRAM 1 Mask reg (r/w) */
 #define        MCFSIM_DCCR1            0x63            /* DRAM 1 Control reg (r/w) */
 
-#define        MCFSIM_PACNT            0x80            /* Port A Control (r/w) */
-#define        MCFSIM_PADDR            0x84            /* Port A Direction (r/w) */
-#define        MCFSIM_PADAT            0x86            /* Port A Data (r/w) */
-#define        MCFSIM_PBCNT            0x88            /* Port B Control (r/w) */
-#define        MCFSIM_PBDDR            0x8c            /* Port B Direction (r/w) */
-#define        MCFSIM_PBDAT            0x8e            /* Port B Data (r/w) */
-#define        MCFSIM_PCDDR            0x94            /* Port C Direction (r/w) */
-#define        MCFSIM_PCDAT            0x96            /* Port C Data (r/w) */
-#define        MCFSIM_PDCNT            0x98            /* Port D Control (r/w) */
+#define        MCFSIM_PACNT            (MCF_MBAR + 0x80) /* Port A Control (r/w) */
+#define        MCFSIM_PADDR            (MCF_MBAR + 0x84) /* Port A Direction (r/w) */
+#define        MCFSIM_PADAT            (MCF_MBAR + 0x86) /* Port A Data (r/w) */
+#define        MCFSIM_PBCNT            (MCF_MBAR + 0x88) /* Port B Control (r/w) */
+#define        MCFSIM_PBDDR            (MCF_MBAR + 0x8c) /* Port B Direction (r/w) */
+#define        MCFSIM_PBDAT            (MCF_MBAR + 0x8e) /* Port B Data (r/w) */
+#define        MCFSIM_PCDDR            (MCF_MBAR + 0x94) /* Port C Direction (r/w) */
+#define        MCFSIM_PCDAT            (MCF_MBAR + 0x96) /* Port C Data (r/w) */
+#define        MCFSIM_PDCNT            (MCF_MBAR + 0x98) /* Port D Control (r/w) */
+
+/*
+ *     Define system peripheral IRQ usage.
+ */
+#define        MCFINT_VECBASE          64              /* Base of interrupts */
+#define        MCF_IRQ_SPURIOUS        64              /* User Spurious */
+#define        MCF_IRQ_EINT1           65              /* External Interrupt 1 */
+#define        MCF_IRQ_EINT2           66              /* External Interrupt 2 */
+#define        MCF_IRQ_EINT3           67              /* External Interrupt 3 */
+#define        MCF_IRQ_EINT4           68              /* External Interrupt 4 */
+#define        MCF_IRQ_TIMER1          69              /* Timer 1 */
+#define        MCF_IRQ_TIMER2          70              /* Timer 2 */
+#define        MCF_IRQ_TIMER3          71              /* Timer 3 */
+#define        MCF_IRQ_TIMER4          72              /* Timer 4 */
+#define        MCF_IRQ_UART1           73              /* UART 1 */
+#define        MCF_IRQ_UART2           74              /* UART 2 */
+#define        MCF_IRQ_PLIP            75              /* PLIC 2Khz Periodic */
+#define        MCF_IRQ_PLIA            76              /* PLIC Asynchronous */
+#define        MCF_IRQ_USB0            77              /* USB Endpoint 0 */
+#define        MCF_IRQ_USB1            78              /* USB Endpoint 1 */
+#define        MCF_IRQ_USB2            79              /* USB Endpoint 2 */
+#define        MCF_IRQ_USB3            80              /* USB Endpoint 3 */
+#define        MCF_IRQ_USB4            81              /* USB Endpoint 4 */
+#define        MCF_IRQ_USB5            82              /* USB Endpoint 5 */
+#define        MCF_IRQ_USB6            83              /* USB Endpoint 6 */
+#define        MCF_IRQ_USB7            84              /* USB Endpoint 7 */
+#define        MCF_IRQ_DMA             85              /* DMA Controller */
+#define        MCF_IRQ_ERX             86              /* Ethernet Receiver */
+#define        MCF_IRQ_ETX             87              /* Ethernet Transmitter */
+#define        MCF_IRQ_ENTC            88              /* Ethernet Non-Time Critical */
+#define        MCF_IRQ_QSPI            89              /* Queued Serial Interface */
+#define        MCF_IRQ_EINT5           90              /* External Interrupt 5 */
+#define        MCF_IRQ_EINT6           91              /* External Interrupt 6 */
+#define        MCF_IRQ_SWTO            92              /* Software Watchdog */
+#define        MCFINT_VECMAX           95              /* Maxmum interrupt */
 
+#define        MCF_IRQ_TIMER           MCF_IRQ_TIMER1
+#define        MCF_IRQ_PROFILER        MCF_IRQ_TIMER2
 
+/*
+ * Generic GPIO support
+ */
+#define MCFGPIO_PIN_MAX                        48
+#define MCFGPIO_IRQ_MAX                        -1
+#define MCFGPIO_IRQ_VECBASE            -1
 /****************************************************************************/
 #endif /* m5272sim_h */