MIPS: Save/restore MSA context around signals

[deliverable/linux.git] / arch / mips / include / asm / cpu.h

diff --git a/arch/mips/include/asm/cpu.h b/arch/mips/include/asm/cpu.h
index d2035e16502a7d98cfe3e015f9855da2617308f2..85e408394336315ced47f1ea9e0c38c54c9b0c55 100644 (file)
--- a/arch/mips/include/asm/cpu.h
+++ b/arch/mips/include/asm/cpu.h
@@ -111,6 +111,10 @@
 #define PRID_IMP_1074K         0x9a00
 #define PRID_IMP_M14KC         0x9c00
 #define PRID_IMP_M14KEC                0x9e00
+#define PRID_IMP_INTERAPTIV_UP 0xa000
+#define PRID_IMP_INTERAPTIV_MP 0xa100
+#define PRID_IMP_PROAPTIV_UP   0xa200
+#define PRID_IMP_PROAPTIV_MP   0xa300
 
 /*
  * These are the PRID's for when 23:16 == PRID_COMP_SIBYTE
@@ -194,6 +198,7 @@
 #define PRID_IMP_NETLOGIC_XLP8XX       0x1000
 #define PRID_IMP_NETLOGIC_XLP3XX       0x1100
 #define PRID_IMP_NETLOGIC_XLP2XX       0x1200
+#define PRID_IMP_NETLOGIC_XLP9XX       0x1500
 
 /*
  * Particular Revision values for bits 7:0 of the PRId register.
@@ -249,6 +254,8 @@
 
 #define FPIR_IMP_NONE          0x0000
 
+#if !defined(__ASSEMBLY__)
+
 enum cpu_type_enum {
        CPU_UNKNOWN,
 
@@ -289,7 +296,7 @@ enum cpu_type_enum {
        CPU_4KC, CPU_4KEC, CPU_4KSC, CPU_24K, CPU_34K, CPU_1004K, CPU_74K,
        CPU_ALCHEMY, CPU_PR4450, CPU_BMIPS32, CPU_BMIPS3300, CPU_BMIPS4350,
        CPU_BMIPS4380, CPU_BMIPS5000, CPU_JZRISC, CPU_LOONGSON1, CPU_M14KC,
-       CPU_M14KEC,
+       CPU_M14KEC, CPU_INTERAPTIV, CPU_PROAPTIV, CPU_1074K,
 
        /*
         * MIPS64 class processors
@@ -301,6 +308,7 @@ enum cpu_type_enum {
        CPU_LAST
 };
 
+#endif /* !__ASSEMBLY */
 
 /*
  * ISA Level encodings
@@ -348,6 +356,8 @@ enum cpu_type_enum {
 #define MIPS_CPU_PCI           0x00400000 /* CPU has Perf Ctr Int indicator */
 #define MIPS_CPU_RIXI          0x00800000 /* CPU has TLB Read/eXec Inhibit */
 #define MIPS_CPU_MICROMIPS     0x01000000 /* CPU has microMIPS capability */
+#define MIPS_CPU_TLBINV                0x02000000 /* CPU supports TLBINV/F */
+#define MIPS_CPU_SEGMENTS      0x04000000 /* CPU supports Segmentation Control registers */
 
 /*
  * CPU ASE encodings
@@ -360,5 +370,6 @@ enum cpu_type_enum {
 #define MIPS_ASE_MIPSMT                0x00000020 /* CPU supports MIPS MT */
 #define MIPS_ASE_DSP2P         0x00000040 /* Signal Processing ASE Rev 2 */
 #define MIPS_ASE_VZ            0x00000080 /* Virtualization ASE */
+#define MIPS_ASE_MSA           0x00000100 /* MIPS SIMD Architecture */
 
 #endif /* _ASM_CPU_H */