" "__beqz"%0, 1b \n"
" nop \n"
" .set pop \n"
- : "=&r" (temp), "=" GCC_OFF12_ASM() (*addr)
- : "ir" (~mask), "ir" (value), GCC_OFF12_ASM() (*addr));
+ : "=&r" (temp), "=" GCC_OFF_SMALL_ASM() (*addr)
+ : "ir" (~mask), "ir" (value), GCC_OFF_SMALL_ASM() (*addr));
}
/*
" "__beqz"%0, 1b \n"
" nop \n"
" .set pop \n"
- : "=&r" (temp), "=" GCC_OFF12_ASM() (*addr)
- : "ir" (mask), GCC_OFF12_ASM() (*addr));
+ : "=&r" (temp), "=" GCC_OFF_SMALL_ASM() (*addr)
+ : "ir" (mask), GCC_OFF_SMALL_ASM() (*addr));
}
/*
" "__beqz"%0, 1b \n"
" nop \n"
" .set pop \n"
- : "=&r" (temp), "=" GCC_OFF12_ASM() (*addr)
- : "ir" (~mask), GCC_OFF12_ASM() (*addr));
+ : "=&r" (temp), "=" GCC_OFF_SMALL_ASM() (*addr)
+ : "ir" (~mask), GCC_OFF_SMALL_ASM() (*addr));
}
/*
" "__beqz"%0, 1b \n"
" nop \n"
" .set pop \n"
- : "=&r" (temp), "=" GCC_OFF12_ASM() (*addr)
- : "ir" (mask), GCC_OFF12_ASM() (*addr));
+ : "=&r" (temp), "=" GCC_OFF_SMALL_ASM() (*addr)
+ : "ir" (mask), GCC_OFF_SMALL_ASM() (*addr));
}
/*
" .set arch=r4000 \n" \
"1: ll %0, %1 #custom_read_reg32 \n" \
" .set pop \n" \
- : "=r" (tmp), "=" GCC_OFF12_ASM() (*address) \
- : GCC_OFF12_ASM() (*address))
+ : "=r" (tmp), "=" GCC_OFF_SMALL_ASM() (*address) \
+ : GCC_OFF_SMALL_ASM() (*address))
#define custom_write_reg32(address, tmp) \
__asm__ __volatile__( \
" "__beqz"%0, 1b \n" \
" nop \n" \
" .set pop \n" \
- : "=&r" (tmp), "=" GCC_OFF12_ASM() (*address) \
- : "0" (tmp), GCC_OFF12_ASM() (*address))
+ : "=&r" (tmp), "=" GCC_OFF_SMALL_ASM() (*address) \
+ : "0" (tmp), GCC_OFF_SMALL_ASM() (*address))
#endif /* __ASM_REGOPS_H__ */