Avoid SMP cacheflushes. This is a minor optimization of startup but

[deliverable/linux.git] / arch / mips / kernel / traps.c

diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c
index 0a3969aa8dc6f548eb04a2a689b613199e43a4d8..519b8f18eedfcafea926b2d0b2aefd809b2b63a8 100644 (file)
--- a/arch/mips/kernel/traps.c
+++ b/arch/mips/kernel/traps.c
@@ -1150,6 +1150,7 @@ static inline void signal32_init(void)
 
 extern void cpu_cache_init(void);
 extern void tlb_init(void);
+extern void flush_tlb_handlers(void);
 
 void __init per_cpu_trap_init(void)
 {
@@ -1348,4 +1349,5 @@ void __init trap_init(void)
 #endif
 
        flush_icache_range(ebase, ebase + 0x400);
+       flush_tlb_handlers();
 }