{
int i;
- for (i = 0; i < MAX_EIU; i++) {
+ for (i = 0; i < exin_avail; i++) {
if (d->hwirq == ltq_eiu_irq[i]) {
int val = 0;
int edge = 0;
int i;
ltq_enable_irq(d);
- for (i = 0; i < MAX_EIU; i++) {
+ for (i = 0; i < exin_avail; i++) {
if (d->hwirq == ltq_eiu_irq[i]) {
/* by default we are low level triggered */
ltq_eiu_settype(d, IRQF_TRIGGER_LOW);
int i;
ltq_disable_irq(d);
- for (i = 0; i < MAX_EIU; i++) {
+ for (i = 0; i < exin_avail; i++) {
if (d->hwirq == ltq_eiu_irq[i]) {
/* disable */
ltq_eiu_w32(ltq_eiu_r32(LTQ_EIU_EXIN_INEN) & ~BIT(i),
}
static struct irq_chip ltq_irq_type = {
- "icu",
+ .name = "icu",
.irq_enable = ltq_enable_irq,
.irq_disable = ltq_disable_irq,
.irq_unmask = ltq_enable_irq,
};
static struct irq_chip ltq_eiu_type = {
- "eiu",
+ .name = "eiu",
.irq_startup = ltq_startup_eiu_irq,
.irq_shutdown = ltq_shutdown_eiu_irq,
.irq_enable = ltq_enable_irq,
if (hw == ltq_eiu_irq[i])
chip = <q_eiu_type;
- irq_set_chip_and_handler(hw, chip, handle_level_irq);
+ irq_set_chip_and_handler(irq, chip, handle_level_irq);
return 0;
}