config MN10300
def_bool y
select HAVE_OPROFILE
- select HAVE_ARCH_TRACEHOOK
-config AM33
- def_bool y
+config AM33_2
+ def_bool n
+
+config AM33_3
+ def_bool n
+
+config AM34_2
+ def_bool n
+ select MN10300_HAS_ATOMIC_OPS_UNIT
+ select MN10300_HAS_CACHE_SNOOP
config MMU
def_bool y
config MN10300_PROC_MN103E010
bool "MN103E010"
depends on MN10300_UNIT_ASB2303 || MN10300_UNIT_ASB2305
+ select AM33_2
select MN10300_PROC_HAS_TTYSM0
select MN10300_PROC_HAS_TTYSM1
select MN10300_PROC_HAS_TTYSM2
endchoice
+config MN10300_HAS_ATOMIC_OPS_UNIT
+ def_bool n
+ help
+ This should be enabled if the processor has an atomic ops unit
+ capable of doing LL/SC equivalent operations.
+
config FPU
bool "FPU present"
default y
depends on MN10300_PROC_MN103E010
-choice
- prompt "CPU Caching mode"
- default MN10300_CACHE_WBACK
- help
- This option determines the caching mode for the kernel.
-
- Write-Back caching mode involves the all reads and writes causing
- the affected cacheline to be read into the cache first before being
- operated upon. Memory is not then updated by a write until the cache
- is filled and a cacheline needs to be displaced from the cache to
- make room. Only at that point is it written back.
-
- Write-Through caching only fetches cachelines from memory on a
- read. Writes always get written directly to memory. If the affected
- cacheline is also in cache, it will be updated too.
-
- The final option is to turn of caching entirely.
-
-config MN10300_CACHE_WBACK
- bool "Write-Back"
-
-config MN10300_CACHE_WTHRU
- bool "Write-Through"
-
-config MN10300_CACHE_DISABLED
- bool "Disabled"
-
-endchoice
+source "arch/mn10300/mm/Kconfig.cache"
menu "Memory layout options"