powerpc/mm: Add SMP support to no-hash TLB handling

[deliverable/linux.git] / arch / powerpc / kernel / misc_32.S

diff --git a/arch/powerpc/kernel/misc_32.S b/arch/powerpc/kernel/misc_32.S
index 6a9b4bf0d173e0f0a656c0ef313af7fed325df59..2c2ab89f0b64af7c6e0e2acd20c3a40916839d63 100644 (file)
--- a/arch/powerpc/kernel/misc_32.S
+++ b/arch/powerpc/kernel/misc_32.S
@@ -29,6 +29,7 @@
 #include <asm/asm-offsets.h>
 #include <asm/processor.h>
 #include <asm/kexec.h>
+#include <asm/bug.h>
 
        .text
 
@@ -470,6 +471,8 @@ _GLOBAL(_tlbil_pid)
        mfspr   r3,SPRN_MMUCSR0
        andi.   r3,r3,MMUCSR0_TLBFI@l
        bne     1b
+       msync
+       isync
        blr
 
 /*
@@ -477,18 +480,31 @@ _GLOBAL(_tlbil_pid)
  * (no broadcast)
  */
 _GLOBAL(_tlbil_va)
+       mfmsr   r10
+       wrteei  0
        slwi    r4,r4,16
        mtspr   SPRN_MAS6,r4            /* assume AS=0 for now */
        tlbsx   0,r3
        mfspr   r4,SPRN_MAS1            /* check valid */
        andis.  r3,r4,MAS1_VALID@h
-       beqlr
+       beq     1f
        rlwinm  r4,r4,0,1,31
        mtspr   SPRN_MAS1,r4
        tlbwe
+       msync
+       isync
+1:     wrtee   r10
        blr
 #endif /* CONFIG_FSL_BOOKE */
 
+/*
+ * Nobody implements this yet
+ */
+_GLOBAL(_tlbivax_bcast)
+1:     trap
+       EMIT_BUG_ENTRY 1b,__FILE__,__LINE__,0;
+       blr
+
 
 /*
  * Flush instruction cache.