[SPARC64]: Probe D/I/E-cache config and use.

[deliverable/linux.git] / arch / sparc64 / kernel / devices.c

diff --git a/arch/sparc64/kernel/devices.c b/arch/sparc64/kernel/devices.c
index d710274e516bf6a400b573473692611b6dbe024c..df9a1ca8fd773ad7e97418bf69fba2428a07aa99 100644 (file)
--- a/arch/sparc64/kernel/devices.c
+++ b/arch/sparc64/kernel/devices.c
@@ -135,6 +135,28 @@ void __init device_scan(void)
                cpu_data(0).clock_tick = prom_getintdefault(cpu_node,
                                                            "clock-frequency",
                                                            0);
+               cpu_data(0).dcache_size = prom_getintdefault(cpu_node,
+                                                            "dcache-size",
+                                                            16 * 1024);
+               cpu_data(0).dcache_line_size =
+                       prom_getintdefault(cpu_node, "dcache-line-size", 32);
+               cpu_data(0).icache_size = prom_getintdefault(cpu_node,
+                                                            "icache-size",
+                                                            16 * 1024);
+               cpu_data(0).icache_line_size =
+                       prom_getintdefault(cpu_node, "icache-line-size", 32);
+               cpu_data(0).ecache_size = prom_getintdefault(cpu_node,
+                                                            "ecache-size",
+                                                            4 * 1024 * 1024);
+               cpu_data(0).ecache_line_size =
+                       prom_getintdefault(cpu_node, "ecache-line-size", 64);
+               printk("CPU[0]: Caches "
+                      "D[sz(%d):line_sz(%d)] "
+                      "I[sz(%d):line_sz(%d)] "
+                      "E[sz(%d):line_sz(%d)]\n",
+                      cpu_data(0).dcache_size, cpu_data(0).dcache_line_size,
+                      cpu_data(0).icache_size, cpu_data(0).icache_line_size,
+                      cpu_data(0).ecache_size, cpu_data(0).ecache_line_size);
        }
 #endif