[SPARC64] PCI: Use common routine to fetch PBM properties.

[deliverable/linux.git] / arch / sparc64 / kernel / pci_sabre.c

diff --git a/arch/sparc64/kernel/pci_sabre.c b/arch/sparc64/kernel/pci_sabre.c
index 2dad171b54e2dceab09112b5fe2f32489ffee5c3..9e706013d11ac8653a378d73a11255779d61f5cc 100644 (file)
--- a/arch/sparc64/kernel/pci_sabre.c
+++ b/arch/sparc64/kernel/pci_sabre.c
@@ -1,7 +1,6 @@
-/* $Id: pci_sabre.c,v 1.42 2002/01/23 11:27:32 davem Exp $
- * pci_sabre.c: Sabre specific PCI controller support.
+/* pci_sabre.c: Sabre specific PCI controller support.
  *
- * Copyright (C) 1997, 1998, 1999 David S. Miller (davem@caipfs.rutgers.edu)
+ * Copyright (C) 1997, 1998, 1999, 2007 David S. Miller (davem@davemloft.net)
  * Copyright (C) 1998, 1999 Eddie C. Dost   (ecd@skynet.be)
  * Copyright (C) 1999 Jakub Jelinek   (jakub@redhat.com)
  */
@@ -319,6 +318,12 @@ static int __sabre_read_pci_cfg(struct pci_bus *bus_dev, unsigned int devfn,
 static int sabre_read_pci_cfg(struct pci_bus *bus, unsigned int devfn,
                              int where, int size, u32 *value)
 {
+       struct pci_pbm_info *pbm = bus->sysdata;
+
+       if (bus == pbm->pci_bus && devfn == 0x00)
+               return pci_host_bridge_read_pci_cfg(bus, devfn, where,
+                                                   size, value);
+
        if (!bus->number && sabre_out_of_range(devfn)) {
                switch (size) {
                case 1:
@@ -435,6 +440,12 @@ static int __sabre_write_pci_cfg(struct pci_bus *bus_dev, unsigned int devfn,
 static int sabre_write_pci_cfg(struct pci_bus *bus, unsigned int devfn,
                               int where, int size, u32 value)
 {
+       struct pci_pbm_info *pbm = bus->sysdata;
+
+       if (bus == pbm->pci_bus && devfn == 0x00)
+               return pci_host_bridge_write_pci_cfg(bus, devfn, where,
+                                                    size, value);
+
        if (bus->number)
                return __sabre_write_pci_cfg(bus, devfn, where, size, value);
 
@@ -487,7 +498,7 @@ static void sabre_check_iommu_error(struct pci_controller_info *p,
                                    unsigned long afsr,
                                    unsigned long afar)
 {
-       struct pci_iommu *iommu = p->pbm_A.iommu;
+       struct iommu *iommu = p->pbm_A.iommu;
        unsigned long iommu_tag[16];
        unsigned long iommu_data[16];
        unsigned long flags;
@@ -862,67 +873,6 @@ static void sabre_register_error_handlers(struct pci_controller_info *p)
        sabre_write(base + SABRE_PCICTRL, tmp);
 }
 
-static void sabre_resource_adjust(struct pci_dev *pdev,
-                                 struct resource *res,
-                                 struct resource *root)
-{
-       struct pci_pbm_info *pbm = pdev->bus->sysdata;
-       unsigned long base;
-
-       if (res->flags & IORESOURCE_IO)
-               base = pbm->controller_regs + SABRE_IOSPACE;
-       else
-               base = pbm->controller_regs + SABRE_MEMSPACE;
-
-       res->start += base;
-       res->end += base;
-}
-
-static void sabre_base_address_update(struct pci_dev *pdev, int resource)
-{
-       struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller;
-       struct resource *res;
-       unsigned long base;
-       u32 reg;
-       int where, size, is_64bit;
-
-       res = &pdev->resource[resource];
-       if (resource < 6) {
-               where = PCI_BASE_ADDRESS_0 + (resource * 4);
-       } else if (resource == PCI_ROM_RESOURCE) {
-               where = pdev->rom_base_reg;
-       } else {
-               /* Somebody might have asked allocation of a non-standard resource */
-               return;
-       }
-
-       is_64bit = 0;
-       if (res->flags & IORESOURCE_IO)
-               base = pbm->controller_regs + SABRE_IOSPACE;
-       else {
-               base = pbm->controller_regs + SABRE_MEMSPACE;
-               if ((res->flags & PCI_BASE_ADDRESS_MEM_TYPE_MASK)
-                   == PCI_BASE_ADDRESS_MEM_TYPE_64)
-                       is_64bit = 1;
-       }
-
-       size = res->end - res->start;
-       pci_read_config_dword(pdev, where, &reg);
-       reg = ((reg & size) |
-              (((u32)(res->start - base)) & ~size));
-       if (resource == PCI_ROM_RESOURCE) {
-               reg |= PCI_ROM_ADDRESS_ENABLE;
-               res->flags |= IORESOURCE_ROM_ENABLE;
-       }
-       pci_write_config_dword(pdev, where, reg);
-
-       /* This knows that the upper 32-bits of the address
-        * must be zero.  Our PCI common layer enforces this.
-        */
-       if (is_64bit)
-               pci_write_config_dword(pdev, where + 4, 0);
-}
-
 static void apb_init(struct pci_controller_info *p, struct pci_bus *sabre_bus)
 {
        struct pci_dev *pdev;
@@ -997,7 +947,7 @@ static void sabre_iommu_init(struct pci_controller_info *p,
                             int tsbsize, unsigned long dvma_offset,
                             u32 dma_mask)
 {
-       struct pci_iommu *iommu = p->pbm_A.iommu;
+       struct iommu *iommu = p->pbm_A.iommu;
        unsigned long i;
        u64 control;
 
@@ -1056,21 +1006,18 @@ static void sabre_pbm_init(struct pci_controller_info *p, struct device_node *dp
        pbm->chip_type = PBM_CHIP_TYPE_SABRE;
        pbm->parent = p;
        pbm->prom_node = dp;
-       pbm->pci_first_slot = 1;
-       pbm->pci_first_busno = p->pci_first_busno;
-       pbm->pci_last_busno = p->pci_last_busno;
+       pci_get_pbm_props(pbm);
 
        pci_determine_mem_io_space(pbm);
 }
 
 void sabre_init(struct device_node *dp, char *model_name)
 {
-       struct linux_prom64_registers *pr_regs;
+       const struct linux_prom64_registers *pr_regs;
        struct pci_controller_info *p;
-       struct pci_iommu *iommu;
+       struct iommu *iommu;
        int tsbsize;
-       u32 *busrange;
-       u32 *vdma;
+       const u32 *vdma;
        u32 upa_portid, dma_mask;
        u64 clear_irq;
 
@@ -1113,10 +1060,7 @@ void sabre_init(struct device_node *dp, char *model_name)
 
        p->pbm_A.portid = upa_portid;
        p->index = pci_num_controllers++;
-       p->pbms_same_domain = 1;
        p->scan_bus = sabre_scan_bus;
-       p->base_address_update = sabre_base_address_update;
-       p->resource_adjust = sabre_resource_adjust;
        p->pci_ops = &sabre_ops;
 
        /*
@@ -1173,10 +1117,6 @@ void sabre_init(struct device_node *dp, char *model_name)
 
        sabre_iommu_init(p, tsbsize, vdma[0], dma_mask);
 
-       busrange = of_get_property(dp, "bus-range", NULL);
-       p->pci_first_busno = busrange[0];
-       p->pci_last_busno = busrange[1];
-
        /*
         * Look for APB underneath.
         */