#include <linux/kdebug.h>
#include <linux/sched.h>
-#include <asm/intel_arch_perfmon.h>
+#include <asm/perf_counter.h>
#include <asm/apic.h>
static bool perf_counters_initialized __read_mostly;
/*
* Number of (generic) HW counters:
*/
-static int nr_hw_counters __read_mostly;
-static u32 perf_counter_mask __read_mostly;
+static int nr_counters_generic __read_mostly;
+static u64 perf_counter_mask __read_mostly;
+static u64 counter_value_mask __read_mostly;
-/* No support for fixed function counters yet */
-
-#define MAX_HW_COUNTERS 8
+static int nr_counters_fixed __read_mostly;
struct cpu_hw_counters {
- struct perf_counter *counters[MAX_HW_COUNTERS];
- unsigned long used[BITS_TO_LONGS(MAX_HW_COUNTERS)];
+ struct perf_counter *counters[X86_PMC_IDX_MAX];
+ unsigned long used[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
+ unsigned long interrupts;
+ u64 global_enable;
};
/*
*/
static DEFINE_PER_CPU(struct cpu_hw_counters, cpu_hw_counters);
-const int intel_perfmon_event_map[] =
+static const int intel_perfmon_event_map[] =
{
- [PERF_COUNT_CYCLES] = 0x003c,
+ [PERF_COUNT_CPU_CYCLES] = 0x003c,
[PERF_COUNT_INSTRUCTIONS] = 0x00c0,
[PERF_COUNT_CACHE_REFERENCES] = 0x4f2e,
[PERF_COUNT_CACHE_MISSES] = 0x412e,
[PERF_COUNT_BRANCH_INSTRUCTIONS] = 0x00c4,
[PERF_COUNT_BRANCH_MISSES] = 0x00c5,
+ [PERF_COUNT_BUS_CYCLES] = 0x013c,
};
-const int max_intel_perfmon_events = ARRAY_SIZE(intel_perfmon_event_map);
+static const int max_intel_perfmon_events = ARRAY_SIZE(intel_perfmon_event_map);
+
+/*
+ * Propagate counter elapsed time into the generic counter.
+ * Can only be executed on the CPU where the counter is active.
+ * Returns the delta events processed.
+ */
+static void
+x86_perf_counter_update(struct perf_counter *counter,
+ struct hw_perf_counter *hwc, int idx)
+{
+ u64 prev_raw_count, new_raw_count, delta;
+
+ /*
+ * Careful: an NMI might modify the previous counter value.
+ *
+ * Our tactic to handle this is to first atomically read and
+ * exchange a new raw count - then add that new-prev delta
+ * count to the generic counter atomically:
+ */
+again:
+ prev_raw_count = atomic64_read(&hwc->prev_count);
+ rdmsrl(hwc->counter_base + idx, new_raw_count);
+
+ if (atomic64_cmpxchg(&hwc->prev_count, prev_raw_count,
+ new_raw_count) != prev_raw_count)
+ goto again;
+
+ /*
+ * Now we have the new raw value and have updated the prev
+ * timestamp already. We can now calculate the elapsed delta
+ * (counter-)time and add that to the generic counter.
+ *
+ * Careful, not all hw sign-extends above the physical width
+ * of the count, so we do that by clipping the delta to 32 bits:
+ */
+ delta = (u64)(u32)((s32)new_raw_count - (s32)prev_raw_count);
+
+ atomic64_add(delta, &counter->count);
+ atomic64_sub(delta, &hwc->period_left);
+}
/*
* Setup the hardware configuration for a given hw_event_type
hwc->nmi = 1;
}
- hwc->config_base = MSR_ARCH_PERFMON_EVENTSEL0;
- hwc->counter_base = MSR_ARCH_PERFMON_PERFCTR0;
-
hwc->irq_period = hw_event->irq_period;
/*
* Intel PMCs cannot be accessed sanely above 32 bit width,
* so we install an artificial 1<<31 period regardless of
* the generic counter period:
*/
- if (!hwc->irq_period)
+ if ((s64)hwc->irq_period <= 0 || hwc->irq_period > 0x7FFFFFFF)
hwc->irq_period = 0x7FFFFFFF;
- hwc->next_count = -(s32)hwc->irq_period;
+ atomic64_set(&hwc->period_left, hwc->irq_period);
/*
* Raw event type provide the config in the event structure
return 0;
}
-void hw_perf_enable_all(void)
+u64 hw_perf_save_disable(void)
{
- wrmsr(MSR_CORE_PERF_GLOBAL_CTRL, perf_counter_mask, 0);
+ u64 ctrl;
+
+ if (unlikely(!perf_counters_initialized))
+ return 0;
+
+ rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL, ctrl);
+ wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0);
+
+ return ctrl;
}
+EXPORT_SYMBOL_GPL(hw_perf_save_disable);
-void hw_perf_restore_ctrl(u64 ctrl)
+void hw_perf_restore(u64 ctrl)
{
- wrmsr(MSR_CORE_PERF_GLOBAL_CTRL, ctrl, 0);
+ if (unlikely(!perf_counters_initialized))
+ return;
+
+ wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, ctrl);
}
-EXPORT_SYMBOL_GPL(hw_perf_restore_ctrl);
+EXPORT_SYMBOL_GPL(hw_perf_restore);
-u64 hw_perf_disable_all(void)
+static inline void
+__pmc_fixed_disable(struct perf_counter *counter,
+ struct hw_perf_counter *hwc, unsigned int __idx)
{
- u64 ctrl;
+ int idx = __idx - X86_PMC_IDX_FIXED;
+ u64 ctrl_val, mask;
+ int err;
- rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL, ctrl);
- wrmsr(MSR_CORE_PERF_GLOBAL_CTRL, 0, 0);
- return ctrl;
+ mask = 0xfULL << (idx * 4);
+
+ rdmsrl(hwc->config_base, ctrl_val);
+ ctrl_val &= ~mask;
+ err = checking_wrmsrl(hwc->config_base, ctrl_val);
}
-EXPORT_SYMBOL_GPL(hw_perf_disable_all);
static inline void
-__x86_perf_counter_disable(struct hw_perf_counter *hwc, unsigned int idx)
+__pmc_generic_disable(struct perf_counter *counter,
+ struct hw_perf_counter *hwc, unsigned int idx)
{
- wrmsr(hwc->config_base + idx, hwc->config, 0);
+ if (unlikely(hwc->config_base == MSR_ARCH_PERFMON_FIXED_CTR_CTRL))
+ __pmc_fixed_disable(counter, hwc, idx);
+ else
+ wrmsr_safe(hwc->config_base + idx, hwc->config, 0);
}
-static DEFINE_PER_CPU(u64, prev_next_count[MAX_HW_COUNTERS]);
+static DEFINE_PER_CPU(u64, prev_left[X86_PMC_IDX_MAX]);
-static void __hw_perf_counter_set_period(struct hw_perf_counter *hwc, int idx)
+/*
+ * Set the next IRQ period, based on the hwc->period_left value.
+ * To be called with the counter disabled in hw:
+ */
+static void
+__hw_perf_counter_set_period(struct perf_counter *counter,
+ struct hw_perf_counter *hwc, int idx)
{
- per_cpu(prev_next_count[idx], smp_processor_id()) = hwc->next_count;
+ s64 left = atomic64_read(&hwc->period_left);
+ s32 period = hwc->irq_period;
+ int err;
+
+ /*
+ * If we are way outside a reasoable range then just skip forward:
+ */
+ if (unlikely(left <= -period)) {
+ left = period;
+ atomic64_set(&hwc->period_left, left);
+ }
- wrmsr(hwc->counter_base + idx, hwc->next_count, 0);
+ if (unlikely(left <= 0)) {
+ left += period;
+ atomic64_set(&hwc->period_left, left);
+ }
+
+ per_cpu(prev_left[idx], smp_processor_id()) = left;
+
+ /*
+ * The hw counter starts counting from this counter offset,
+ * mark it to be able to extra future deltas:
+ */
+ atomic64_set(&hwc->prev_count, (u64)-left);
+
+ err = checking_wrmsrl(hwc->counter_base + idx,
+ (u64)(-left) & counter_value_mask);
}
-static void __x86_perf_counter_enable(struct hw_perf_counter *hwc, int idx)
+static inline void
+__pmc_fixed_enable(struct perf_counter *counter,
+ struct hw_perf_counter *hwc, unsigned int __idx)
{
- wrmsr(hwc->config_base + idx,
- hwc->config | ARCH_PERFMON_EVENTSEL0_ENABLE, 0);
+ int idx = __idx - X86_PMC_IDX_FIXED;
+ u64 ctrl_val, bits, mask;
+ int err;
+
+ /*
+ * Enable IRQ generation (0x8) and ring-3 counting (0x2),
+ * and enable ring-0 counting if allowed:
+ */
+ bits = 0x8ULL | 0x2ULL;
+ if (hwc->config & ARCH_PERFMON_EVENTSEL_OS)
+ bits |= 0x1;
+ bits <<= (idx * 4);
+ mask = 0xfULL << (idx * 4);
+
+ rdmsrl(hwc->config_base, ctrl_val);
+ ctrl_val &= ~mask;
+ ctrl_val |= bits;
+ err = checking_wrmsrl(hwc->config_base, ctrl_val);
}
-static void x86_perf_counter_enable(struct perf_counter *counter)
+static void
+__pmc_generic_enable(struct perf_counter *counter,
+ struct hw_perf_counter *hwc, int idx)
{
- struct cpu_hw_counters *cpuc = &__get_cpu_var(cpu_hw_counters);
- struct hw_perf_counter *hwc = &counter->hw;
- int idx = hwc->idx;
+ if (unlikely(hwc->config_base == MSR_ARCH_PERFMON_FIXED_CTR_CTRL))
+ __pmc_fixed_enable(counter, hwc, idx);
+ else
+ wrmsr(hwc->config_base + idx,
+ hwc->config | ARCH_PERFMON_EVENTSEL0_ENABLE, 0);
+}
- /* Try to get the previous counter again */
- if (test_and_set_bit(idx, cpuc->used)) {
- idx = find_first_zero_bit(cpuc->used, nr_hw_counters);
- set_bit(idx, cpuc->used);
- hwc->idx = idx;
- }
+static int
+fixed_mode_idx(struct perf_counter *counter, struct hw_perf_counter *hwc)
+{
+ unsigned int event;
- perf_counters_lapic_init(hwc->nmi);
+ if (unlikely(hwc->nmi))
+ return -1;
- __x86_perf_counter_disable(hwc, idx);
+ event = hwc->config & ARCH_PERFMON_EVENT_MASK;
- cpuc->counters[idx] = counter;
+ if (unlikely(event == intel_perfmon_event_map[PERF_COUNT_INSTRUCTIONS]))
+ return X86_PMC_IDX_FIXED_INSTRUCTIONS;
+ if (unlikely(event == intel_perfmon_event_map[PERF_COUNT_CPU_CYCLES]))
+ return X86_PMC_IDX_FIXED_CPU_CYCLES;
+ if (unlikely(event == intel_perfmon_event_map[PERF_COUNT_BUS_CYCLES]))
+ return X86_PMC_IDX_FIXED_BUS_CYCLES;
- __hw_perf_counter_set_period(hwc, idx);
- __x86_perf_counter_enable(hwc, idx);
+ return -1;
}
-static void __hw_perf_save_counter(struct perf_counter *counter,
- struct hw_perf_counter *hwc, int idx)
+/*
+ * Find a PMC slot for the freshly enabled / scheduled in counter:
+ */
+static int pmc_generic_enable(struct perf_counter *counter)
{
- s64 raw = -1;
- s64 delta;
+ struct cpu_hw_counters *cpuc = &__get_cpu_var(cpu_hw_counters);
+ struct hw_perf_counter *hwc = &counter->hw;
+ int idx;
- /*
- * Get the raw hw counter value:
- */
- rdmsrl(hwc->counter_base + idx, raw);
+ idx = fixed_mode_idx(counter, hwc);
+ if (idx >= 0) {
+ /*
+ * Try to get the fixed counter, if that is already taken
+ * then try to get a generic counter:
+ */
+ if (test_and_set_bit(idx, cpuc->used))
+ goto try_generic;
- /*
- * Rebase it to zero (it started counting at -irq_period),
- * to see the delta since ->prev_count:
- */
- delta = (s64)hwc->irq_period + (s64)(s32)raw;
+ hwc->config_base = MSR_ARCH_PERFMON_FIXED_CTR_CTRL;
+ /*
+ * We set it so that counter_base + idx in wrmsr/rdmsr maps to
+ * MSR_ARCH_PERFMON_FIXED_CTR0 ... CTR2:
+ */
+ hwc->counter_base =
+ MSR_ARCH_PERFMON_FIXED_CTR0 - X86_PMC_IDX_FIXED;
+ hwc->idx = idx;
+ } else {
+ idx = hwc->idx;
+ /* Try to get the previous generic counter again */
+ if (test_and_set_bit(idx, cpuc->used)) {
+try_generic:
+ idx = find_first_zero_bit(cpuc->used, nr_counters_generic);
+ if (idx == nr_counters_generic)
+ return -EAGAIN;
+
+ set_bit(idx, cpuc->used);
+ hwc->idx = idx;
+ }
+ hwc->config_base = MSR_ARCH_PERFMON_EVENTSEL0;
+ hwc->counter_base = MSR_ARCH_PERFMON_PERFCTR0;
+ }
- atomic64_counter_set(counter, hwc->prev_count + delta);
+ perf_counters_lapic_init(hwc->nmi);
- /*
- * Adjust the ->prev_count offset - if we went beyond
- * irq_period of units, then we got an IRQ and the counter
- * was set back to -irq_period:
- */
- while (delta >= (s64)hwc->irq_period) {
- hwc->prev_count += hwc->irq_period;
- delta -= (s64)hwc->irq_period;
- }
+ __pmc_generic_disable(counter, hwc, idx);
+ cpuc->counters[idx] = counter;
/*
- * Calculate the next raw counter value we'll write into
- * the counter at the next sched-in time:
+ * Make it visible before enabling the hw:
*/
- delta -= (s64)hwc->irq_period;
+ smp_wmb();
+
+ __hw_perf_counter_set_period(counter, hwc, idx);
+ __pmc_generic_enable(counter, hwc, idx);
- hwc->next_count = (s32)delta;
+ return 0;
}
void perf_counter_print_debug(void)
{
- u64 ctrl, status, overflow, pmc_ctrl, pmc_count, next_count;
+ u64 ctrl, status, overflow, pmc_ctrl, pmc_count, prev_left, fixed;
+ struct cpu_hw_counters *cpuc;
int cpu, idx;
- if (!nr_hw_counters)
+ if (!nr_counters_generic)
return;
local_irq_disable();
cpu = smp_processor_id();
+ cpuc = &per_cpu(cpu_hw_counters, cpu);
rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL, ctrl);
rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status);
rdmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, overflow);
+ rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR_CTRL, fixed);
printk(KERN_INFO "\n");
printk(KERN_INFO "CPU#%d: ctrl: %016llx\n", cpu, ctrl);
printk(KERN_INFO "CPU#%d: status: %016llx\n", cpu, status);
printk(KERN_INFO "CPU#%d: overflow: %016llx\n", cpu, overflow);
+ printk(KERN_INFO "CPU#%d: fixed: %016llx\n", cpu, fixed);
+ printk(KERN_INFO "CPU#%d: used: %016llx\n", cpu, *(u64 *)cpuc->used);
- for (idx = 0; idx < nr_hw_counters; idx++) {
+ for (idx = 0; idx < nr_counters_generic; idx++) {
rdmsrl(MSR_ARCH_PERFMON_EVENTSEL0 + idx, pmc_ctrl);
rdmsrl(MSR_ARCH_PERFMON_PERFCTR0 + idx, pmc_count);
- next_count = per_cpu(prev_next_count[idx], cpu);
+ prev_left = per_cpu(prev_left[idx], cpu);
- printk(KERN_INFO "CPU#%d: PMC%d ctrl: %016llx\n",
+ printk(KERN_INFO "CPU#%d: gen-PMC%d ctrl: %016llx\n",
cpu, idx, pmc_ctrl);
- printk(KERN_INFO "CPU#%d: PMC%d count: %016llx\n",
+ printk(KERN_INFO "CPU#%d: gen-PMC%d count: %016llx\n",
+ cpu, idx, pmc_count);
+ printk(KERN_INFO "CPU#%d: gen-PMC%d left: %016llx\n",
+ cpu, idx, prev_left);
+ }
+ for (idx = 0; idx < nr_counters_fixed; idx++) {
+ rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, pmc_count);
+
+ printk(KERN_INFO "CPU#%d: fixed-PMC%d count: %016llx\n",
cpu, idx, pmc_count);
- printk(KERN_INFO "CPU#%d: PMC%d next: %016llx\n",
- cpu, idx, next_count);
}
local_irq_enable();
}
-static void x86_perf_counter_disable(struct perf_counter *counter)
+static void pmc_generic_disable(struct perf_counter *counter)
{
struct cpu_hw_counters *cpuc = &__get_cpu_var(cpu_hw_counters);
struct hw_perf_counter *hwc = &counter->hw;
unsigned int idx = hwc->idx;
- __x86_perf_counter_disable(hwc, idx);
+ __pmc_generic_disable(counter, hwc, idx);
clear_bit(idx, cpuc->used);
cpuc->counters[idx] = NULL;
- __hw_perf_save_counter(counter, hwc, idx);
-}
+ /*
+ * Make sure the cleared pointer becomes visible before we
+ * (potentially) free the counter:
+ */
+ smp_wmb();
-static void x86_perf_counter_read(struct perf_counter *counter)
-{
- struct hw_perf_counter *hwc = &counter->hw;
- unsigned long addr = hwc->counter_base + hwc->idx;
- s64 offs, val = -1LL;
- s32 val32;
-
- /* Careful: NMI might modify the counter offset */
- do {
- offs = hwc->prev_count;
- rdmsrl(addr, val);
- } while (offs != hwc->prev_count);
-
- val32 = (s32) val;
- val = (s64)hwc->irq_period + (s64)val32;
- atomic64_counter_set(counter, hwc->prev_count + val);
+ /*
+ * Drain the remaining delta count out of a counter
+ * that we are disabling:
+ */
+ x86_perf_counter_update(counter, hwc, idx);
}
static void perf_store_irq_data(struct perf_counter *counter, u64 data)
}
/*
- * NMI-safe enable method:
+ * Save and restart an expired counter. Called by NMI contexts,
+ * so it has to be careful about preempting normal counter ops:
*/
static void perf_save_and_restart(struct perf_counter *counter)
{
struct hw_perf_counter *hwc = &counter->hw;
int idx = hwc->idx;
- u64 pmc_ctrl;
- rdmsrl(MSR_ARCH_PERFMON_EVENTSEL0 + idx, pmc_ctrl);
+ x86_perf_counter_update(counter, hwc, idx);
+ __hw_perf_counter_set_period(counter, hwc, idx);
- __hw_perf_save_counter(counter, hwc, idx);
- __hw_perf_counter_set_period(hwc, idx);
-
- if (pmc_ctrl & ARCH_PERFMON_EVENTSEL0_ENABLE)
- __x86_perf_counter_enable(hwc, idx);
+ if (counter->state == PERF_COUNTER_STATE_ACTIVE)
+ __pmc_generic_enable(counter, hwc, idx);
}
static void
perf_handle_group(struct perf_counter *sibling, u64 *status, u64 *overflown)
{
struct perf_counter *counter, *group_leader = sibling->group_leader;
- int bit;
/*
- * Store the counter's own timestamp first:
- */
- perf_store_irq_data(sibling, sibling->hw_event.type);
- perf_store_irq_data(sibling, atomic64_counter_read(sibling));
-
- /*
- * Then store sibling timestamps (if any):
+ * Store sibling timestamps (if any):
*/
list_for_each_entry(counter, &group_leader->sibling_list, list_entry) {
- if (!counter->active) {
- /*
- * When counter was not in the overflow mask, we have to
- * read it from hardware. We read it as well, when it
- * has not been read yet and clear the bit in the
- * status mask.
- */
- bit = counter->hw.idx;
- if (!test_bit(bit, (unsigned long *) overflown) ||
- test_bit(bit, (unsigned long *) status)) {
- clear_bit(bit, (unsigned long *) status);
- perf_save_and_restart(counter);
- }
- }
+
+ x86_perf_counter_update(counter, &counter->hw, counter->hw.idx);
perf_store_irq_data(sibling, counter->hw_event.type);
- perf_store_irq_data(sibling, atomic64_counter_read(counter));
+ perf_store_irq_data(sibling, atomic64_read(&counter->count));
}
}
+/*
+ * Maximum interrupt frequency of 100KHz per CPU
+ */
+#define PERFMON_MAX_INTERRUPTS 100000/HZ
+
/*
* This handler is triggered by the local APIC, so the APIC IRQ handling
* rules apply:
static void __smp_perf_counter_interrupt(struct pt_regs *regs, int nmi)
{
int bit, cpu = smp_processor_id();
- u64 ack, status, saved_global;
- struct cpu_hw_counters *cpuc;
+ u64 ack, status;
+ struct cpu_hw_counters *cpuc = &per_cpu(cpu_hw_counters, cpu);
- rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL, saved_global);
+ rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL, cpuc->global_enable);
/* Disable counters globally */
- wrmsr(MSR_CORE_PERF_GLOBAL_CTRL, 0, 0);
+ wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0);
ack_APIC_irq();
- cpuc = &per_cpu(cpu_hw_counters, cpu);
-
rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status);
if (!status)
goto out;
again:
+ inc_irq_stat(apic_perf_irqs);
ack = status;
- for_each_bit(bit, (unsigned long *) &status, nr_hw_counters) {
+ for_each_bit(bit, (unsigned long *)&status, X86_PMC_IDX_MAX) {
struct perf_counter *counter = cpuc->counters[bit];
clear_bit(bit, (unsigned long *) &status);
}
/*
* From NMI context we cannot call into the scheduler to
- * do a task wakeup - but we mark these counters as
+ * do a task wakeup - but we mark these generic as
* wakeup_pending and initate a wakeup callback:
*/
if (nmi) {
}
}
- wrmsr(MSR_CORE_PERF_GLOBAL_OVF_CTRL, ack, 0);
+ wrmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, ack);
/*
* Repeat if there is more work to be done:
goto again;
out:
/*
- * Restore - do not reenable when global enable is off:
+ * Restore - do not reenable when global enable is off or throttled:
*/
- wrmsr(MSR_CORE_PERF_GLOBAL_CTRL, saved_global, 0);
+ if (++cpuc->interrupts < PERFMON_MAX_INTERRUPTS)
+ wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, cpuc->global_enable);
+}
+
+void perf_counter_unthrottle(void)
+{
+ struct cpu_hw_counters *cpuc;
+ u64 global_enable;
+
+ if (!cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON))
+ return;
+
+ if (unlikely(!perf_counters_initialized))
+ return;
+
+ cpuc = &per_cpu(cpu_hw_counters, smp_processor_id());
+ if (cpuc->interrupts >= PERFMON_MAX_INTERRUPTS) {
+ if (printk_ratelimit())
+ printk(KERN_WARNING "PERFMON: max interrupts exceeded!\n");
+ wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, cpuc->global_enable);
+ }
+ rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL, global_enable);
+ if (unlikely(cpuc->global_enable && !global_enable))
+ wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, cpuc->global_enable);
+ cpuc->interrupts = 0;
}
void smp_perf_counter_interrupt(struct pt_regs *regs)
{
irq_enter();
-#ifdef CONFIG_X86_64
- add_pda(apic_perf_irqs, 1);
-#else
- per_cpu(irq_stat, smp_processor_id()).apic_perf_irqs++;
-#endif
apic_write(APIC_LVTPC, LOCAL_PERF_VECTOR);
__smp_perf_counter_interrupt(regs, 0);
cpu = smp_processor_id();
cpuc = &per_cpu(cpu_hw_counters, cpu);
- for_each_bit(bit, cpuc->used, nr_hw_counters) {
+ for_each_bit(bit, cpuc->used, X86_PMC_IDX_MAX) {
struct perf_counter *counter = cpuc->counters[bit];
if (!counter)
local_irq_restore(flags);
}
-void __cpuinit perf_counters_lapic_init(int nmi)
+void perf_counters_lapic_init(int nmi)
{
u32 apic_val;
}
static __read_mostly struct notifier_block perf_counter_nmi_notifier = {
- .notifier_call = perf_counter_nmi_handler
+ .notifier_call = perf_counter_nmi_handler,
+ .next = NULL,
+ .priority = 1
};
void __init init_hw_perf_counters(void)
{
union cpuid10_eax eax;
- unsigned int unused;
unsigned int ebx;
+ unsigned int unused;
+ union cpuid10_edx edx;
if (!cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON))
return;
* Check whether the Architectural PerfMon supports
* Branch Misses Retired Event or not.
*/
- cpuid(10, &(eax.full), &ebx, &unused, &unused);
+ cpuid(10, &eax.full, &ebx, &unused, &edx.full);
if (eax.split.mask_length <= ARCH_PERFMON_BRANCH_MISSES_RETIRED)
return;
printk(KERN_INFO "Intel Performance Monitoring support detected.\n");
- printk(KERN_INFO "... version: %d\n", eax.split.version_id);
- printk(KERN_INFO "... num_counters: %d\n", eax.split.num_counters);
- nr_hw_counters = eax.split.num_counters;
- if (nr_hw_counters > MAX_HW_COUNTERS) {
- nr_hw_counters = MAX_HW_COUNTERS;
+ printk(KERN_INFO "... version: %d\n", eax.split.version_id);
+ printk(KERN_INFO "... num counters: %d\n", eax.split.num_counters);
+ nr_counters_generic = eax.split.num_counters;
+ if (nr_counters_generic > X86_PMC_MAX_GENERIC) {
+ nr_counters_generic = X86_PMC_MAX_GENERIC;
WARN(1, KERN_ERR "hw perf counters %d > max(%d), clipping!",
- nr_hw_counters, MAX_HW_COUNTERS);
+ nr_counters_generic, X86_PMC_MAX_GENERIC);
+ }
+ perf_counter_mask = (1 << nr_counters_generic) - 1;
+ perf_max_counters = nr_counters_generic;
+
+ printk(KERN_INFO "... bit width: %d\n", eax.split.bit_width);
+ counter_value_mask = (1ULL << eax.split.bit_width) - 1;
+ printk(KERN_INFO "... value mask: %016Lx\n", counter_value_mask);
+
+ printk(KERN_INFO "... mask length: %d\n", eax.split.mask_length);
+
+ nr_counters_fixed = edx.split.num_counters_fixed;
+ if (nr_counters_fixed > X86_PMC_MAX_FIXED) {
+ nr_counters_fixed = X86_PMC_MAX_FIXED;
+ WARN(1, KERN_ERR "hw perf counters fixed %d > max(%d), clipping!",
+ nr_counters_fixed, X86_PMC_MAX_FIXED);
}
- perf_counter_mask = (1 << nr_hw_counters) - 1;
- perf_max_counters = nr_hw_counters;
+ printk(KERN_INFO "... fixed counters: %d\n", nr_counters_fixed);
+
+ perf_counter_mask |= ((1LL << nr_counters_fixed)-1) << X86_PMC_IDX_FIXED;
- printk(KERN_INFO "... bit_width: %d\n", eax.split.bit_width);
- printk(KERN_INFO "... mask_length: %d\n", eax.split.mask_length);
+ printk(KERN_INFO "... counter mask: %016Lx\n", perf_counter_mask);
+ perf_counters_initialized = true;
perf_counters_lapic_init(0);
register_die_notifier(&perf_counter_nmi_notifier);
+}
- perf_counters_initialized = true;
+static void pmc_generic_read(struct perf_counter *counter)
+{
+ x86_perf_counter_update(counter, &counter->hw, counter->hw.idx);
}
static const struct hw_perf_counter_ops x86_perf_counter_ops = {
- .hw_perf_counter_enable = x86_perf_counter_enable,
- .hw_perf_counter_disable = x86_perf_counter_disable,
- .hw_perf_counter_read = x86_perf_counter_read,
+ .enable = pmc_generic_enable,
+ .disable = pmc_generic_disable,
+ .read = pmc_generic_read,
};
const struct hw_perf_counter_ops *
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