x86/cpu: Convert printk(KERN_<LEVEL> ...) to pr_<level>(...)

[deliverable/linux.git] / arch / x86 / kernel / cpu / perf_event_amd_ibs.c

diff --git a/arch/x86/kernel/cpu/perf_event_amd_ibs.c b/arch/x86/kernel/cpu/perf_event_amd_ibs.c
index 989d3c215d2bcea3b1a55bc2e8a42d9e20b31a98..aa12f9509cfbfbace5f667020143db841afb1311 100644 (file)
--- a/arch/x86/kernel/cpu/perf_event_amd_ibs.c
+++ b/arch/x86/kernel/cpu/perf_event_amd_ibs.c
@@ -670,7 +670,7 @@ static __init int perf_event_ibs_init(void)
        perf_ibs_pmu_init(&perf_ibs_op, "ibs_op");
 
        register_nmi_handler(NMI_LOCAL, perf_ibs_nmi_handler, 0, "perf_ibs");
-       printk(KERN_INFO "perf: AMD IBS detected (0x%08x)\n", ibs_caps);
+       pr_info("perf: AMD IBS detected (0x%08x)\n", ibs_caps);
 
        return 0;
 }
@@ -774,14 +774,14 @@ static int setup_ibs_ctl(int ibs_eilvt_off)
                pci_read_config_dword(cpu_cfg, IBSCTL, &value);
                if (value != (ibs_eilvt_off | IBSCTL_LVT_OFFSET_VALID)) {
                        pci_dev_put(cpu_cfg);
-                       printk(KERN_DEBUG "Failed to setup IBS LVT offset, "
-                              "IBSCTL = 0x%08x\n", value);
+                       pr_debug("Failed to setup IBS LVT offset, IBSCTL = 0x%08x\n",
+                                value);
                        return -EINVAL;
                }
        } while (1);
 
        if (!nodes) {
-               printk(KERN_DEBUG "No CPU node configured for IBS\n");
+               pr_debug("No CPU node configured for IBS\n");
                return -ENODEV;
        }
 
@@ -810,7 +810,7 @@ static void force_ibs_eilvt_setup(void)
        preempt_enable();
 
        if (offset == APIC_EILVT_NR_MAX) {
-               printk(KERN_DEBUG "No EILVT entry available\n");
+               pr_debug("No EILVT entry available\n");
                return;
        }