static DEFINE_SPINLOCK(ioapic_lock);
static DEFINE_SPINLOCK(vector_lock);
-int first_free_entry;
-/*
- * Rough estimation of how many shared IRQs there are, can
- * be changed anytime.
- */
-int pin_map_size;
-
/*
* # of IRQ routing registers
*/
struct irq_pin_list;
struct irq_cfg {
unsigned int irq;
+#ifdef CONFIG_HAVE_SPARSE_IRQ
struct irq_cfg *next;
+#endif
struct irq_pin_list *irq_2_pin;
cpumask_t domain;
cpumask_t old_domain;
};
static struct irq_cfg irq_cfg_init = { .irq = -1U, };
-/* need to be biger than size of irq_cfg_legacy */
-static int nr_irq_cfg = 32;
-
-static int __init parse_nr_irq_cfg(char *arg)
-{
- if (arg) {
- nr_irq_cfg = simple_strtoul(arg, NULL, 0);
- if (nr_irq_cfg < 32)
- nr_irq_cfg = 32;
- }
- return 0;
-}
-
-early_param("nr_irq_cfg", parse_nr_irq_cfg);
static void init_one_irq_cfg(struct irq_cfg *cfg)
{
}
static struct irq_cfg *irq_cfgx;
+
+/*
+ * Protect the irq_cfgx_free freelist:
+ */
+static DEFINE_SPINLOCK(irq_cfg_lock);
+
+#ifdef CONFIG_HAVE_SPARSE_IRQ
static struct irq_cfg *irq_cfgx_free;
+#endif
static void __init init_work(void *data)
{
struct dyn_array *da = data;
for (i = legacy_count; i < *da->nr; i++)
init_one_irq_cfg(&cfg[i]);
+#ifdef CONFIG_HAVE_SPARSE_IRQ
for (i = 1; i < *da->nr; i++)
cfg[i-1].next = &cfg[i];
irq_cfgx_free = &irq_cfgx[legacy_count];
irq_cfgx[legacy_count - 1].next = NULL;
+#endif
}
-#define for_each_irq_cfg(cfg) \
- for (cfg = irq_cfgx; cfg; cfg = cfg->next)
+#ifdef CONFIG_HAVE_SPARSE_IRQ
+/* need to be biger than size of irq_cfg_legacy */
+static int nr_irq_cfg = 32;
+
+static int __init parse_nr_irq_cfg(char *arg)
+{
+ if (arg) {
+ nr_irq_cfg = simple_strtoul(arg, NULL, 0);
+ if (nr_irq_cfg < 32)
+ nr_irq_cfg = 32;
+ }
+ return 0;
+}
+
+early_param("nr_irq_cfg", parse_nr_irq_cfg);
+
+#define for_each_irq_cfg(irqX, cfg) \
+ for (cfg = irq_cfgx, irqX = cfg->irq; cfg; cfg = cfg->next, irqX = cfg ? cfg->irq : -1U)
+
DEFINE_DYN_ARRAY(irq_cfgx, sizeof(struct irq_cfg), nr_irq_cfg, PAGE_SIZE, init_work);
static struct irq_cfg *irq_cfg_alloc(unsigned int irq)
{
struct irq_cfg *cfg, *cfg_pri;
- int i;
+ unsigned long flags;
int count = 0;
+ int i;
cfg_pri = cfg = irq_cfgx;
while (cfg) {
count++;
}
+ spin_lock_irqsave(&irq_cfg_lock, flags);
if (!irq_cfgx_free) {
unsigned long phys;
unsigned long total_bytes;
else
irq_cfgx = cfg;
cfg->irq = irq;
+
+ spin_unlock_irqrestore(&irq_cfg_lock, flags);
+
printk(KERN_DEBUG "found new irq_cfg for irq %d\n", cfg->irq);
#ifdef CONFIG_HAVE_SPARSE_IRQ_DEBUG
{
#endif
return cfg;
}
+#else
+
+#define for_each_irq_cfg(irq, cfg) \
+ for (irq = 0, cfg = &irq_cfgx[irq]; irq < nr_irqs; irq++, cfg = &irq_cfgx[irq])
+DEFINE_DYN_ARRAY(irq_cfgx, sizeof(struct irq_cfg), nr_irqs, PAGE_SIZE, init_work);
+
+struct irq_cfg *irq_cfg(unsigned int irq)
+{
+ if (irq < nr_irqs)
+ return &irq_cfgx[irq];
+
+ return NULL;
+}
+struct irq_cfg *irq_cfg_alloc(unsigned int irq)
+{
+ return irq_cfg(irq);
+}
+
+#endif
/*
* This is performance-critical, we want to do it O(1)
*
struct irq_cfg *cfg;
/* Mark the inuse vectors */
- for_each_irq_cfg(cfg) {
+ for_each_irq_cfg(irq, cfg) {
if (!cpu_isset(cpu, cfg->domain))
continue;
vector = cfg->vector;
- irq = cfg->irq;
per_cpu(vector_irq, cpu)[vector] = irq;
}
/* Mark the free vectors */
union IO_APIC_reg_03 reg_03;
unsigned long flags;
struct irq_cfg *cfg;
+ unsigned int irq;
if (apic_verbosity == APIC_QUIET)
return;
}
}
printk(KERN_DEBUG "IRQ to pin mappings:\n");
- for_each_irq_cfg(cfg) {
+ for_each_irq_cfg(irq, cfg) {
struct irq_pin_list *entry = cfg->irq_2_pin;
if (!entry)
continue;
- printk(KERN_DEBUG "IRQ%d ", cfg->irq);
+ printk(KERN_DEBUG "IRQ%d ", irq);
for (;;) {
printk("-> %d:%d", entry->apic, entry->pin);
if (!entry->next)
}
icr = apic_icr_read();
- printk(KERN_DEBUG "... APIC ICR: %08x\n", icr);
- printk(KERN_DEBUG "... APIC ICR2: %08x\n", icr >> 32);
+ printk(KERN_DEBUG "... APIC ICR: %08x\n", (u32)icr);
+ printk(KERN_DEBUG "... APIC ICR2: %08x\n", (u32)(icr >> 32));
v = apic_read(APIC_LVTT);
printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
__apicdebuginit(void) print_all_local_APICs(void)
{
- on_each_cpu(print_local_APIC, NULL, 1);
+ int cpu;
+
+ preempt_disable();
+ for_each_online_cpu(cpu)
+ smp_call_function_single(cpu, print_local_APIC, NULL, 1);
+ preempt_enable();
}
__apicdebuginit(void) print_PIC(void)
reg_00.bits.ID = mp_ioapics[apic].mp_apicid;
spin_lock_irqsave(&ioapic_lock, flags);
+ io_apic_write(apic, 0, reg_00.raw);
+ spin_unlock_irqrestore(&ioapic_lock, flags);
/*
* Sanity check
* Also, we've got to be careful not to trash gate
* 0x80, because int 0x80 is hm, kind of importantish. ;)
*/
- for_each_irq_cfg(cfg) {
- irq = cfg->irq;
+ for_each_irq_cfg(irq, cfg) {
if (IO_APIC_IRQ(irq) && !cfg->vector) {
/*
* Hmm.. We don't have an entry for this,
}
#endif /* CONFIG_HT_IRQ */
+int __init io_apic_get_redir_entries (int ioapic)
+{
+ union IO_APIC_reg_01 reg_01;
+ unsigned long flags;
+
+ spin_lock_irqsave(&ioapic_lock, flags);
+ reg_01.raw = io_apic_read(ioapic, 1);
+ spin_unlock_irqrestore(&ioapic_lock, flags);
+
+ return reg_01.bits.entries;
+}
+
+int __init probe_nr_irqs(void)
+{
+ int idx;
+ int nr = 0;
+#ifndef CONFIG_XEN
+ int nr_min = 32;
+#else
+ int nr_min = NR_IRQS;
+#endif
+
+ for (idx = 0; idx < nr_ioapics; idx++)
+ nr += io_apic_get_redir_entries(idx) + 1;
+
+ /* double it for hotplug and msi and nmi */
+ nr <<= 1;
+
+ /* something wrong ? */
+ if (nr < nr_min)
+ nr = nr_min;
+
+ return nr;
+}
+
/* --------------------------------------------------------------------------
ACPI-based IOAPIC Configuration
-------------------------------------------------------------------------- */
}
#endif
-int __init io_apic_get_redir_entries (int ioapic)
-{
- union IO_APIC_reg_01 reg_01;
- unsigned long flags;
-
- spin_lock_irqsave(&ioapic_lock, flags);
- reg_01.raw = io_apic_read(ioapic, 1);
- spin_unlock_irqrestore(&ioapic_lock, flags);
-
- return reg_01.bits.entries;
-}
-
-
int io_apic_set_pci_routing (int ioapic, int pin, int irq, int triggering, int polarity)
{
if (!IO_APIC_IRQ(irq)) {
projects / deliverable / linux.git / blobdiff