KVM: Remove internal timer abstraction

[deliverable/linux.git] / arch / x86 / kvm / lapic.h

diff --git a/arch/x86/kvm/lapic.h b/arch/x86/kvm/lapic.h
index 6f4ce2575d095edce570b7d15c0cd9724b6255ec..d7251c92ed426ef96cb48a74edc958cf45fe69ee 100644 (file)
--- a/arch/x86/kvm/lapic.h
+++ b/arch/x86/kvm/lapic.h
@@ -2,10 +2,25 @@
 #define __KVM_X86_LAPIC_H
 
 #include "iodev.h"
-#include "kvm_timer.h"
 
 #include <linux/kvm_host.h>
 
+struct kvm_timer {
+       struct hrtimer timer;
+       s64 period;                             /* unit: ns */
+       u32 timer_mode_mask;
+       u64 tscdeadline;
+       atomic_t pending;                       /* accumulated triggered timers */
+       bool reinject;
+       struct kvm_timer_ops *t_ops;
+       struct kvm *kvm;
+       struct kvm_vcpu *vcpu;
+};
+
+struct kvm_timer_ops {
+       bool (*is_periodic)(struct kvm_timer *);
+};
+
 struct kvm_lapic {
        unsigned long base_address;
        struct kvm_io_device dev;
@@ -13,6 +28,15 @@ struct kvm_lapic {
        u32 divide_count;
        struct kvm_vcpu *vcpu;
        bool irr_pending;
+       /* Number of bits set in ISR. */
+       s16 isr_count;
+       /* The highest vector set in ISR; if -1 - invalid, must scan ISR. */
+       int highest_isr_cache;
+       /**
+        * APIC register page.  The layout matches the register layout seen by
+        * the guest 1:1, because it is accessed by the vmx microcode.
+        * Note: Only one register, the TPR, is used by the microcode.
+        */
        void *regs;
        gpa_t vapic_addr;
        struct page *vapic_page;
@@ -60,4 +84,6 @@ static inline bool kvm_hv_vapic_assist_page_enabled(struct kvm_vcpu *vcpu)
 {
        return vcpu->arch.hv_vapic & HV_X64_MSR_APIC_ASSIST_PAGE_ENABLE;
 }
+
+int kvm_lapic_enable_pv_eoi(struct kvm_vcpu *vcpu, u64 data);
 #endif