.#define bfd_mach_mcf5307 11
.#define bfd_mach_mcf5407 12
.#define bfd_mach_mcf528x 13
+.#define bfd_mach_mcfv4e 14
+.#define bfd_mach_mcf521x 15
+.#define bfd_mach_mcf5249 16
+.#define bfd_mach_mcf547x 17
+.#define bfd_mach_mcf548x 18
. bfd_arch_vax, {* DEC Vax *}
. bfd_arch_i960, {* Intel 960 *}
. {* The order of the following is important.
.#define bfd_mach_sparc_v9_p(mach) \
. ((mach) >= bfd_mach_sparc_v8plus && (mach) <= bfd_mach_sparc_v9b \
. && (mach) != bfd_mach_sparc_sparclite_le)
+.{* Nonzero if MACH is a 64 bit sparc architecture. *}
+.#define bfd_mach_sparc_64bit_p(mach) \
+. ((mach) >= bfd_mach_sparc_v9 && (mach) != bfd_mach_sparc_v8plusb)
. bfd_arch_mips, {* MIPS Rxxxx *}
.#define bfd_mach_mips3000 3000
.#define bfd_mach_mips3900 3900
.#define bfd_mach_sh 1
.#define bfd_mach_sh2 0x20
.#define bfd_mach_sh_dsp 0x2d
+.#define bfd_mach_sh2a 0x2a
+.#define bfd_mach_sh2a_nofpu 0x2b
.#define bfd_mach_sh2e 0x2e
.#define bfd_mach_sh3 0x30
+.#define bfd_mach_sh3_nommu 0x31
.#define bfd_mach_sh3_dsp 0x3d
.#define bfd_mach_sh3e 0x3e
.#define bfd_mach_sh4 0x40
.#define bfd_mach_avr5 5
. bfd_arch_cr16c, {* National Semiconductor CompactRISC. *}
.#define bfd_mach_cr16c 1
+. bfd_arch_crx, {* National Semiconductor CRX. *}
+.#define bfd_mach_crx 1
. bfd_arch_cris, {* Axis CRIS *}
. bfd_arch_s390, {* IBM s390 *}
.#define bfd_mach_s390_31 31
extern const bfd_arch_info_type bfd_avr_arch;
extern const bfd_arch_info_type bfd_cr16c_arch;
extern const bfd_arch_info_type bfd_cris_arch;
+extern const bfd_arch_info_type bfd_crx_arch;
extern const bfd_arch_info_type bfd_d10v_arch;
extern const bfd_arch_info_type bfd_d30v_arch;
extern const bfd_arch_info_type bfd_dlx_arch;
&bfd_avr_arch,
&bfd_cr16c_arch,
&bfd_cris_arch,
+ &bfd_crx_arch,
&bfd_d10v_arch,
&bfd_d30v_arch,
&bfd_dlx_arch,