#define bfd_mach_sparc_v9_p(mach) \
((mach) >= bfd_mach_sparc_v8plus && (mach) <= bfd_mach_sparc_v9a)
bfd_arch_mips, /* MIPS Rxxxx */
+#define bfd_mach_mips3000 3000
+#define bfd_mach_mips6000 6000
+#define bfd_mach_mips4000 4000
+#define bfd_mach_mips8000 8000
+#define bfd_mach_mips16 16
+ /* start-sanitize-vr5400 */
+#define bfd_mach_vr5400 5400
+#define bfd_mach_vr5000 5000
+ /* end-sanitize-vr5400 */
bfd_arch_i386, /* Intel 386 */
#define bfd_mach_i386_i386 0
#define bfd_mach_i386_i8086 1
/* start-sanitize-tic80 */
bfd_arch_tic80, /* TI TMS320c80 (MVP) */
/* end-sanitize-tic80 */
+ /* start-sanitize-sky */
+ bfd_arch_txvu, /* TX VU */
+#define bfd_mach_txvu 0
+ /* end-sanitize-sky */
bfd_arch_v850, /* NEC V850 */
#define bfd_mach_v850 0
/* start-sanitize-v850e */
#define bfd_mach_v850e 'E'
+#define bfd_mach_v850ea 'A'
/* end-sanitize-v850e */
- /* start-sanitize-v850eq */
-#define bfd_mach_v850eq 'Q'
- /* end-sanitize-v850eq */
bfd_arch_arc, /* Argonaut RISC Core */
#define bfd_mach_arc_base 0
bfd_arch_m32r, /* Mitsubishi M32R/D */
+#define bfd_mach_m32r 0 /* backwards compatibility */
+ /* start-sanitize-m32rx */
+#define bfd_mach_m32rx 'x'
+ /* end-sanitize-m32rx */
bfd_arch_mn10200, /* Matsushita MN10200 */
bfd_arch_mn10300, /* Matsushita MN10300 */
bfd_arch_last
const bfd_arch_info_type *
bfd_scan_arch PARAMS ((const char *string));
+const char **
+bfd_arch_list PARAMS ((void));
+
const bfd_arch_info_type *
bfd_arch_get_compatible PARAMS ((
const bfd *abfd,
} arelent_chain;
bfd_reloc_status_type
+bfd_check_overflow
+ PARAMS ((enum complain_overflow how,
+ unsigned int bitsize,
+ unsigned int rightshift,
+ bfd_vma relocation));
+
+bfd_reloc_status_type
+
bfd_perform_relocation
PARAMS ((bfd *abfd,
arelent *reloc_entry,
BFD_RELOC_SPARC_BASE13,
BFD_RELOC_SPARC_BASE22,
-/* Some relocations we're using for SPARC V9 -- subject to change. */
+/* SPARC64 relocations */
#define BFD_RELOC_SPARC_64 BFD_RELOC_64
BFD_RELOC_SPARC_10,
BFD_RELOC_SPARC_11,
BFD_RELOC_SPARC_PC_LM22,
BFD_RELOC_SPARC_WDISP16,
BFD_RELOC_SPARC_WDISP19,
- BFD_RELOC_SPARC_GLOB_JMP,
BFD_RELOC_SPARC_7,
BFD_RELOC_SPARC_6,
BFD_RELOC_SPARC_5,
+#define BFD_RELOC_SPARC_DISP64 BFD_RELOC_64_PCREL
+ BFD_RELOC_SPARC_PLT64,
+ BFD_RELOC_SPARC_HIX22,
+ BFD_RELOC_SPARC_LOX10,
+ BFD_RELOC_SPARC_H44,
+ BFD_RELOC_SPARC_M44,
+ BFD_RELOC_SPARC_L44,
+ BFD_RELOC_SPARC_REGISTER,
/* Alpha ECOFF and ELF relocations. Some of these treat the symbol or
"addend" in some special way.
This is a 6-bit absolute reloc. */
BFD_RELOC_D30V_6,
-/* Mitsubishi D30V relocs.
-This is a 12-bit absolute reloc with the
+/* This is a 6-bit pc-relative reloc with
+the right 3 bits assumed to be 0. */
+ BFD_RELOC_D30V_9_PCREL,
+
+/* This is a 6-bit pc-relative reloc with
+the right 3 bits assumed to be 0. Same
+as the previous reloc but on the right side
+of the container. */
+ BFD_RELOC_D30V_9_PCREL_R,
+
+/* This is a 12-bit absolute reloc with the
right 3 bitsassumed to be 0. */
BFD_RELOC_D30V_15,
-/* Mitsubishi D30V relocs.
-This is a 12-bit pc-relative reloc with
+/* This is a 12-bit pc-relative reloc with
the right 3 bits assumed to be 0. */
BFD_RELOC_D30V_15_PCREL,
+/* This is a 12-bit pc-relative reloc with
+the right 3 bits assumed to be 0. Same
+as the previous reloc but on the right side
+of the container. */
+ BFD_RELOC_D30V_15_PCREL_R,
+
/* This is an 18-bit absolute reloc with
the right 3 bits assumed to be 0. */
BFD_RELOC_D30V_21,
the right 3 bits assumed to be 0. */
BFD_RELOC_D30V_21_PCREL,
+/* This is an 18-bit pc-relative reloc with
+the right 3 bits assumed to be 0. Same
+as the previous reloc but on the right side
+of the container. */
+ BFD_RELOC_D30V_21_PCREL_R,
+
/* This is a 32-bit absolute reloc. */
BFD_RELOC_D30V_32,
/* This is a 7 bit offset from the tiny data area pointer. */
BFD_RELOC_V850_TDA_7_7_OFFSET,
+
+/* This is a 16 bit offset from the tiny data area pointer. */
+ BFD_RELOC_V850_TDA_16_16_OFFSET,
/* start-sanitize-v850e */
/* This is a 5 bit offset (of which only 4 bits are used) from the tiny
/* This is a 16 bit offset from the zero data area pointer, with the
bits placed non-contigously in the instruction. */
BFD_RELOC_V850_ZDA_16_16_SPLIT_OFFSET,
+
+/* This is a 6 bit offset from the call table base pointer. */
+ BFD_RELOC_V850_CALLT_6_7_OFFSET,
+
+/* This is a 16 bit offset from the call table base pointer. */
+ BFD_RELOC_V850_CALLT_16_16_OFFSET,
/* end-sanitize-v850e */