/* DO NOT EDIT! -*- buffer-read-only: t -*- This file is automatically
generated from "bfd-in.h", "init.c", "opncls.c", "libbfd.c",
"section.c", "archures.c", "reloc.c", "syms.c", "bfd.c", "archive.c",
- "corefile.c", "targets.c" and "format.c".
+ "corefile.c", "targets.c", "format.c", "linker.c" and "simple.c".
Run "make headers" in your build bfd/ to regenerate. */
/* Main header file for the bfd library -- portable access to object files.
#endif
#endif
-#define BFD_VERSION @bfd_version@
-#define BFD_VERSION_DATE @bfd_version_date@
-#define BFD_VERSION_STRING @bfd_version_string@
-
/* The word size used by BFD on the host. This may be 64 with a 32
bit target if the host is 64 bit, or if other 64 bit targets have
been selected with --enable-targets, or if --enable-64-bit-bfd. */
/* This flag indicates that the BFD contents are actually cached in
memory. If this is set, iostream points to a bfd_in_memory struct. */
#define BFD_IN_MEMORY 0x800
+
+/* The sections in this BFD specify a memory page. */
+#define HAS_LOAD_PAGE 0x1000
\f
/* Symbols and relocation. */
/* Object and core file sections. */
#define align_power(addr, align) \
- ( ((addr) + ((1<<(align))-1)) & (-1 << (align)))
+ (((addr) + ((bfd_vma) 1 << (align)) - 1) & ((bfd_vma) -1 << (align)))
typedef struct sec *sec_ptr;
#define bfd_get_outsymbols(abfd) ((abfd)->outsymbols)
#define bfd_count_sections(abfd) ((abfd)->section_count)
+#define bfd_get_dynamic_symcount(abfd) ((abfd)->dynsymcount)
+
#define bfd_get_symbol_leading_char(abfd) ((abfd)->xvec->symbol_leading_char)
#define bfd_set_cacheable(abfd,bool) (((abfd)->cacheable = (boolean) (bool)), true)
#define bfd_mach_mips4010 4010
#define bfd_mach_mips4100 4100
#define bfd_mach_mips4111 4111
+#define bfd_mach_mips4120 4120
#define bfd_mach_mips4300 4300
#define bfd_mach_mips4400 4400
#define bfd_mach_mips4600 4600
#define bfd_mach_mips4650 4650
#define bfd_mach_mips5000 5000
+#define bfd_mach_mips5400 5400
+#define bfd_mach_mips5500 5500
#define bfd_mach_mips6000 6000
#define bfd_mach_mips8000 8000
#define bfd_mach_mips10000 10000
#define bfd_mach_mipsisa32 32
#define bfd_mach_mipsisa64 64
bfd_arch_i386, /* Intel 386 */
-#define bfd_mach_i386_i386 0
-#define bfd_mach_i386_i8086 1
-#define bfd_mach_i386_i386_intel_syntax 2
-#define bfd_mach_x86_64 3
-#define bfd_mach_x86_64_intel_syntax 4
+#define bfd_mach_i386_i386 1
+#define bfd_mach_i386_i8086 2
+#define bfd_mach_i386_i386_intel_syntax 3
+#define bfd_mach_x86_64 64
+#define bfd_mach_x86_64_intel_syntax 65
bfd_arch_we32k, /* AT&T WE32xxx */
bfd_arch_tahoe, /* CCI/Harris Tahoe */
bfd_arch_i860, /* Intel 860 */
#define bfd_mach_h8300s 3
bfd_arch_pdp11, /* DEC PDP-11 */
bfd_arch_powerpc, /* PowerPC */
-#define bfd_mach_ppc 0
-#define bfd_mach_ppc64 1
+#define bfd_mach_ppc 32
+#define bfd_mach_ppc64 64
#define bfd_mach_ppc_403 403
#define bfd_mach_ppc_403gc 4030
#define bfd_mach_ppc_505 505
#define bfd_mach_ppc_rs64ii 642
#define bfd_mach_ppc_rs64iii 643
#define bfd_mach_ppc_7400 7400
+#define bfd_mach_ppc_e500 500
bfd_arch_rs6000, /* IBM RS/6000 */
-#define bfd_mach_rs6k 0
+#define bfd_mach_rs6k 6000
#define bfd_mach_rs6k_rs1 6001
#define bfd_mach_rs6k_rsc 6003
#define bfd_mach_rs6k_rs2 6002
bfd_arch_hppa, /* HP PA RISC */
bfd_arch_d10v, /* Mitsubishi D10V */
-#define bfd_mach_d10v 0
+#define bfd_mach_d10v 1
#define bfd_mach_d10v_ts2 2
#define bfd_mach_d10v_ts3 3
bfd_arch_d30v, /* Mitsubishi D30V */
#define bfd_mach_z8002 2
bfd_arch_h8500, /* Hitachi H8/500 */
bfd_arch_sh, /* Hitachi SH */
-#define bfd_mach_sh 0
+#define bfd_mach_sh 1
#define bfd_mach_sh2 0x20
#define bfd_mach_sh_dsp 0x2d
#define bfd_mach_sh3 0x30
bfd_arch_ns32k, /* National Semiconductors ns32000 */
bfd_arch_w65, /* WDC 65816 */
bfd_arch_tic30, /* Texas Instruments TMS320C30 */
+ bfd_arch_tic4x, /* Texas Instruments TMS320C3X/4X */
+#define bfd_mach_c3x 30
+#define bfd_mach_c4x 40
bfd_arch_tic54x, /* Texas Instruments TMS320C54X */
bfd_arch_tic80, /* TI TMS320c80 (MVP) */
bfd_arch_v850, /* NEC V850 */
-#define bfd_mach_v850 0
+#define bfd_mach_v850 1
#define bfd_mach_v850e 'E'
-#define bfd_mach_v850ea 'A'
bfd_arch_arc, /* ARC Cores */
-#define bfd_mach_arc_5 0
-#define bfd_mach_arc_6 1
-#define bfd_mach_arc_7 2
-#define bfd_mach_arc_8 3
+#define bfd_mach_arc_5 5
+#define bfd_mach_arc_6 6
+#define bfd_mach_arc_7 7
+#define bfd_mach_arc_8 8
bfd_arch_m32r, /* Mitsubishi M32R/D */
-#define bfd_mach_m32r 0 /* For backwards compatibility. */
+#define bfd_mach_m32r 1 /* For backwards compatibility. */
#define bfd_mach_m32rx 'x'
bfd_arch_mn10200, /* Matsushita MN10200 */
bfd_arch_mn10300, /* Matsushita MN10300 */
bfd_arch_fr30,
#define bfd_mach_fr30 0x46523330
bfd_arch_frv,
-#define bfd_mach_frv 0
-#define bfd_mach_frvsimple 1
+#define bfd_mach_frv 1
+#define bfd_mach_frvsimple 2
#define bfd_mach_fr300 300
#define bfd_mach_fr400 400
#define bfd_mach_frvtomcat 499 /* fr500 prototype */
#define bfd_mach_fr500 500
bfd_arch_mcore,
bfd_arch_ia64, /* HP/Intel ia64 */
-#define bfd_mach_ia64_elf64 0
-#define bfd_mach_ia64_elf32 1
+#define bfd_mach_ia64_elf64 64
+#define bfd_mach_ia64_elf32 32
bfd_arch_ip2k, /* Ubicom IP2K microcontrollers. */
-#define bfd_mach_ip2022 0
-#define bfd_mach_ip2022ext 1
+#define bfd_mach_ip2022 1
+#define bfd_mach_ip2022ext 2
bfd_arch_pj,
bfd_arch_avr, /* Atmel AVR microcontrollers. */
#define bfd_mach_avr1 1
#define bfd_mach_avr5 5
bfd_arch_cris, /* Axis CRIS */
bfd_arch_s390, /* IBM s390 */
-#define bfd_mach_s390_31 0
-#define bfd_mach_s390_64 1
+#define bfd_mach_s390_31 31
+#define bfd_mach_s390_64 64
bfd_arch_openrisc, /* OpenRISC */
bfd_arch_mmix, /* Donald Knuth's educational processor. */
bfd_arch_xstormy16,
-#define bfd_mach_xstormy16 0
+#define bfd_mach_xstormy16 1
bfd_arch_last
};
BFD_RELOC_386_RELATIVE,
BFD_RELOC_386_GOTOFF,
BFD_RELOC_386_GOTPC,
+ BFD_RELOC_386_TLS_TPOFF,
+ BFD_RELOC_386_TLS_IE,
+ BFD_RELOC_386_TLS_GOTIE,
BFD_RELOC_386_TLS_LE,
BFD_RELOC_386_TLS_GD,
BFD_RELOC_386_TLS_LDM,
BFD_RELOC_X86_64_RELATIVE,
BFD_RELOC_X86_64_GOTPCREL,
BFD_RELOC_X86_64_32S,
+ BFD_RELOC_X86_64_DTPMOD64,
+ BFD_RELOC_X86_64_DTPOFF64,
+ BFD_RELOC_X86_64_TPOFF64,
+ BFD_RELOC_X86_64_TLSGD,
+ BFD_RELOC_X86_64_TLSLD,
+ BFD_RELOC_X86_64_DTPOFF32,
+ BFD_RELOC_X86_64_GOTTPOFF,
+ BFD_RELOC_X86_64_TPOFF32,
/* ns32k relocations */
BFD_RELOC_NS32K_IMM_8,
BFD_RELOC_SH_IMM_HI16,
BFD_RELOC_SH_IMM_HI16_PCREL,
BFD_RELOC_SH_PT_16,
+ BFD_RELOC_SH_TLS_GD_32,
+ BFD_RELOC_SH_TLS_LD_32,
+ BFD_RELOC_SH_TLS_LDO_32,
+ BFD_RELOC_SH_TLS_IE_32,
+ BFD_RELOC_SH_TLS_LE_32,
+ BFD_RELOC_SH_TLS_DTPMOD32,
+ BFD_RELOC_SH_TLS_DTPOFF32,
+ BFD_RELOC_SH_TLS_TPOFF32,
/* Thumb 23-, 12- and 9-bit pc-relative branches. The lowest bit must
be zero and is not stored in the instruction. */
/* This is a 16 bit offset from the call table base pointer. */
BFD_RELOC_V850_CALLT_16_16_OFFSET,
+/* Used for relaxing indirect function calls. */
+ BFD_RELOC_V850_LONGCALL,
+
+/* Used for relaxing indirect jumps. */
+ BFD_RELOC_V850_LONGJUMP,
+
+/* Used to maintain alignment whilst relaxing. */
+ BFD_RELOC_V850_ALIGN,
/* This is a 32bit pcrel reloc for the mn10300, offset by two bytes in the
instruction. */
BFD_RELOC_IA64_LTOFF_DTPREL22,
/* Motorola 68HC11 reloc.
-This is the 8 bits high part of an absolute address. */
+This is the 8 bit high part of an absolute address. */
BFD_RELOC_M68HC11_HI8,
/* Motorola 68HC11 reloc.
-This is the 8 bits low part of an absolute address. */
+This is the 8 bit low part of an absolute address. */
BFD_RELOC_M68HC11_LO8,
/* Motorola 68HC11 reloc.
-This is the 3 bits of a value. */
+This is the 3 bit of a value. */
BFD_RELOC_M68HC11_3B,
+/* Motorola 68HC11 reloc.
+This reloc marks the beginning of a jump/call instruction.
+It is used for linker relaxation to correctly identify beginning
+of instruction and change some branchs to use PC-relative
+addressing mode. */
+ BFD_RELOC_M68HC11_RL_JUMP,
+
+/* Motorola 68HC11 reloc.
+This reloc marks a group of several instructions that gcc generates
+and for which the linker relaxation pass can modify and/or remove
+some of them. */
+ BFD_RELOC_M68HC11_RL_GROUP,
+
+/* Motorola 68HC11 reloc.
+This is the 16-bit lower part of an address. It is used for 'call'
+instruction to specify the symbol address without any special
+transformation (due to memory bank window). */
+ BFD_RELOC_M68HC11_LO16,
+
+/* Motorola 68HC11 reloc.
+This is a 8-bit reloc that specifies the page number of an address.
+It is used by 'call' instruction to specify the page number of
+the symbol. */
+ BFD_RELOC_M68HC11_PAGE,
+
+/* Motorola 68HC11 reloc.
+This is a 24-bit reloc that represents the address with a 16-bit
+value and a 8-bit page number. The symbol address is transformed
+to follow the 16K memory bank of 68HC12 (seen as mapped in the window). */
+ BFD_RELOC_M68HC11_24,
+
/* These relocs are only used within the CRIS assembler. They are not
(at present) written to any object files. */
BFD_RELOC_CRIS_BDISP8,
/* Symbol table for output BFD (with symcount entries). */
struct symbol_cache_entry **outsymbols;
+ /* Used for slurped dynamic symbol tables. */
+ unsigned int dynsymcount;
+
/* Pointer to structure which contains architecture information. */
const struct bfd_arch_info *arch_info;
const char *
bfd_format_string PARAMS ((bfd_format format));
+/* Extracted from linker.c. */
+boolean
+bfd_link_split_section PARAMS ((bfd *abfd, asection *sec));
+
+#define bfd_link_split_section(abfd, sec) \
+ BFD_SEND (abfd, _bfd_link_split_section, (abfd, sec))
+
+/* Extracted from simple.c. */
+bfd_byte *
+bfd_simple_get_relocated_section_contents PARAMS ((bfd *abfd, asection *sec, bfd_byte *outbuf));
+
#ifdef __cplusplus
}
#endif