/* A unique sequence number. */
unsigned int id;
+ /* A unique section number which can be used by assembler to
+ distinguish different sections with the same section name. */
+ unsigned int section_id;
+
/* Which section in the bfd; 0..n-1 as sections are created in a bfd. */
unsigned int index;
else up the line will take care of it later. */
#define SEC_LINKER_CREATED 0x100000
+ /* This section contains a section ID to distinguish different
+ sections with the same section name. */
+#define SEC_ASSEMBLER_SECTION_ID 0x100000
+
/* This section should not be subject to garbage collection.
Also set to inform the linker that this section should not be
listed in the link map as discarded. */
/* Early in the link process, map_head and map_tail are used to build
a list of input sections attached to an output section. Later,
output sections use these fields for a list of bfd_link_order
- structs. */
+ structs. The linked_to_symbol_name field is for ELF assembler
+ internal use. */
union {
struct bfd_link_order *link_order;
struct bfd_section *s;
+ const char *linked_to_symbol_name;
} map_head, map_tail;
} asection;
}
#define BFD_FAKE_SECTION(SEC, SYM, NAME, IDX, FLAGS) \
- /* name, id, index, next, prev, flags, user_set_vma, */ \
- { NAME, IDX, 0, NULL, NULL, FLAGS, 0, \
+ /* name, id, section_id, index, next, prev, flags, user_set_vma, */ \
+ { NAME, IDX, 0, 0, NULL, NULL, FLAGS, 0, \
\
/* linker_mark, linker_has_input, gc_mark, decompress_status, */ \
0, 0, 1, 0, \
#define bfd_mach_h8300sx 6
#define bfd_mach_h8300sxn 7
bfd_arch_pdp11, /* DEC PDP-11. */
- bfd_arch_plugin,
bfd_arch_powerpc, /* PowerPC. */
#define bfd_mach_ppc 32
#define bfd_mach_ppc64 64
bfd_arch_xtensa, /* Tensilica's Xtensa cores. */
#define bfd_mach_xtensa 1
bfd_arch_z80,
-#define bfd_mach_z80strict 1 /* No undocumented opcodes. */
-#define bfd_mach_z80 3 /* With ixl, ixh, iyl, and iyh. */
-#define bfd_mach_z80full 7 /* All undocumented instructions. */
-#define bfd_mach_r800 11 /* R800: successor with multiplication. */
+/* Zilog Z80 without undocumented opcodes. */
+#define bfd_mach_z80strict 1
+/* Zilog Z180: successor with additional instructions, but without
+ halves of ix and iy. */
+#define bfd_mach_z180 2
+/* Zilog Z80 with ixl, ixh, iyl, and iyh. */
+#define bfd_mach_z80 3
+/* Zilog eZ80 (successor of Z80 & Z180) in Z80 (16-bit address) mode. */
+#define bfd_mach_ez80_z80 4
+/* Zilog eZ80 (successor of Z80 & Z180) in ADL (24-bit address) mode. */
+#define bfd_mach_ez80_adl 5
+/* Z80N */
+#define bfd_mach_z80n 6
+/* Zilog Z80 with all undocumented instructions. */
+#define bfd_mach_z80full 7
+/* GameBoy Z80 (reduced instruction set). */
+#define bfd_mach_gbz80 8
+/* ASCII R800: successor with multiplication. */
+#define bfd_mach_r800 11
bfd_arch_lm32, /* Lattice Mico32. */
#define bfd_mach_lm32 1
bfd_arch_microblaze,/* Xilinx MicroBlaze. */
/* 8 bit signed offset in (ix+d) or (iy+d). */
BFD_RELOC_Z80_DISP8,
+/* First 8 bits of multibyte (32, 24 or 16 bit) value. */
+ BFD_RELOC_Z80_BYTE0,
+
+/* Second 8 bits of multibyte (32, 24 or 16 bit) value. */
+ BFD_RELOC_Z80_BYTE1,
+
+/* Third 8 bits of multibyte (32 or 24 bit) value. */
+ BFD_RELOC_Z80_BYTE2,
+
+/* Fourth 8 bits of multibyte (32 bit) value. */
+ BFD_RELOC_Z80_BYTE3,
+
+/* Lowest 16 bits of multibyte (32 or 24 bit) value. */
+ BFD_RELOC_Z80_WORD0,
+
+/* Highest 16 bits of multibyte (32 or 24 bit) value. */
+ BFD_RELOC_Z80_WORD1,
+
+/* Like BFD_RELOC_16 but big-endian. */
+ BFD_RELOC_Z80_16_BE,
+
/* DJNZ offset. */
BFD_RELOC_Z8K_DISP7,