PARAMS ((bfd *, struct symbol_cache_entry *, int, union internal_auxent *));
extern boolean bfd_coff_set_symbol_class
- PARAMS ((bfd *, struct symbol_cache_entry *, unsigned char));
+ PARAMS ((bfd *, struct symbol_cache_entry *, unsigned int));
/* ARM Interworking support. Called from linker. */
extern boolean bfd_arm_allocate_interworking_sections
extern boolean bfd_arm_get_bfd_for_interworking
PARAMS ((bfd *, struct bfd_link_info *));
+/* ELF ARM Interworking support. Called from linker. */
+ extern boolean bfd_elf32_arm_allocate_interworking_sections
+ PARAMS ((struct bfd_link_info *));
+
+ extern boolean bfd_elf32_arm_process_before_allocation
+ PARAMS ((bfd *, struct bfd_link_info *));
+
+ extern boolean bfd_elf32_arm_get_bfd_for_interworking
+ PARAMS ((bfd *, struct bfd_link_info *));
+
/* And more from the source. */
void
bfd_init PARAMS ((void));
#define bfd_mach_mips4900 4900
/* end-sanitize-tx49 */
#define bfd_mach_mips5000 5000
- /* start-sanitize-vr5400 */
+ /* start-sanitize-cygnus */
#define bfd_mach_mips5400 5400
- /* end-sanitize-vr5400 */
+ /* end-sanitize-cygnus */
/* start-sanitize-r5900 */
#define bfd_mach_mips5900 5900
/* end-sanitize-r5900 */
bfd_arch_rs6000, /* IBM RS/6000 */
bfd_arch_hppa, /* HP PA RISC */
bfd_arch_d10v, /* Mitsubishi D10V */
- /* start-sanitize-d30v */
bfd_arch_d30v, /* Mitsubishi D30V */
- /* end-sanitize-d30v */
bfd_arch_z8k, /* Zilog Z8000 */
#define bfd_mach_z8001 1
#define bfd_mach_z8002 2
#define bfd_mach_sh3e 0x3e
#define bfd_mach_sh4 0x40
bfd_arch_alpha, /* Dec Alpha */
+#define bfd_mach_alpha_ev4 0x10
+#define bfd_mach_alpha_ev5 0x20
+#define bfd_mach_alpha_ev6 0x30
bfd_arch_arm, /* Advanced Risc Machines ARM */
#define bfd_mach_arm_2 1
#define bfd_mach_arm_2a 2
/* start-sanitize-am33 */
#define bfd_mach_am33 330
/* end-sanitize-am33 */
+ bfd_arch_fr30,
+#define bfd_mach_fr30 0x46523330
bfd_arch_last
};
BFD_RELOC_SPARC_REGISTER,
/* SPARC little endian relocation */
- BFD_RELOC_SPARC_32LE,
+ BFD_RELOC_SPARC_REV32,
/* Alpha ECOFF and ELF relocations. Some of these treat the symbol or
"addend" in some special way.
/* This is a 27 bit address left shifted by 4. */
BFD_RELOC_MIPS_DVP_27_S4,
+
+/* This is the 11 bit offset operand of ilw/stw instructions
+left shifted by 4. */
+ BFD_RELOC_MIPS_DVP_11_S4,
+
+/* This is the 15 bit unsigned immediate operand of the iaddiu instruction
+left shifted by 3. */
+ BFD_RELOC_MIPS_DVP_U15_S3,
/* end-sanitize-sky */
assumed to be 0. */
BFD_RELOC_D10V_18_PCREL,
-/* start-sanitize-d30v */
-
/* Mitsubishi D30V relocs.
This is a 6-bit absolute reloc. */
BFD_RELOC_D30V_6,
/* This is a 32-bit pc-relative reloc. */
BFD_RELOC_D30V_32_PCREL,
-/* end-sanitize-d30v */
-
/* Mitsubishi M32R relocs.
This is a 24 bit absolute address. */
significant 8 bits of the opcode. */
BFD_RELOC_TIC30_LDP,
+/* This is a 32 bit reloc for the FR30 that stores 20 bits split up into
+two sections. */
+ BFD_RELOC_FR30_20,
+
+/* This is a 16 bit reloc for the FR30 that stores a 6 bit word offset in
+4 bits. */
+ BFD_RELOC_FR30_6_IN_4,
+
+/* This is a 16 bit reloc for the FR30 that stores an 8 bit byte offset
+into 8 bits. */
+ BFD_RELOC_FR30_8_IN_8,
+
+/* This is a 16 bit reloc for the FR30 that stores a 9 bit short offset
+into 8 bits. */
+ BFD_RELOC_FR30_9_IN_8,
+
+/* This is a 16 bit reloc for the FR30 that stores a 10 bit word offset
+into 8 bits. */
+ BFD_RELOC_FR30_10_IN_8,
+
+/* This is a 16 bit reloc for the FR30 that stores a 9 bit pc relative
+short offset into 8 bits. */
+ BFD_RELOC_FR30_9_PCREL,
+
+/* This is a 16 bit reloc for the FR30 that stores a 12 bit pc relative
+short offset into 11 bits. */
+ BFD_RELOC_FR30_12_PCREL,
+
/* These two relocations are used by the linker to determine which of
the entries in a C++ virtual function table are actually used. When
the --gc-sections option is given, the linker will zero out the entries
bfd_target_os9k_flavour,
bfd_target_versados_flavour,
bfd_target_msdos_flavour,
+ bfd_target_ovax_flavour,
bfd_target_evax_flavour
};