#define bfd_mach_v850 0
/* start-sanitize-v850e */
#define bfd_mach_v850e 'E'
- /* end-sanitize-v850e */
- /* start-sanitize-v850eq */
#define bfd_mach_v850eq 'Q'
- /* end-sanitize-v850eq */
+ /* end-sanitize-v850e */
bfd_arch_arc, /* Argonaut RISC Core */
#define bfd_mach_arc_base 0
bfd_arch_m32r, /* Mitsubishi M32R/D */
} arelent_chain;
bfd_reloc_status_type
+bfd_check_overflow
+ PARAMS ((enum complain_overflow how,
+ unsigned int bitsize,
+ unsigned int rightshift,
+ bfd_vma value));
+
+bfd_reloc_status_type
+
bfd_perform_relocation
PARAMS ((bfd *abfd,
arelent *reloc_entry,
BFD_RELOC_SPARC_BASE13,
BFD_RELOC_SPARC_BASE22,
-/* Some relocations we're using for SPARC V9 -- subject to change. */
+/* SPARC64 relocations */
#define BFD_RELOC_SPARC_64 BFD_RELOC_64
BFD_RELOC_SPARC_10,
BFD_RELOC_SPARC_11,
BFD_RELOC_SPARC_PC_LM22,
BFD_RELOC_SPARC_WDISP16,
BFD_RELOC_SPARC_WDISP19,
- BFD_RELOC_SPARC_GLOB_JMP,
BFD_RELOC_SPARC_7,
BFD_RELOC_SPARC_6,
BFD_RELOC_SPARC_5,
+#define BFD_RELOC_SPARC_DISP64 BFD_RELOC_64_PCREL
+ BFD_RELOC_SPARC_PLT64,
+ BFD_RELOC_SPARC_HIX22,
+ BFD_RELOC_SPARC_LOX10,
+ BFD_RELOC_SPARC_H44,
+ BFD_RELOC_SPARC_M44,
+ BFD_RELOC_SPARC_L44,
+ BFD_RELOC_SPARC_REGISTER,
/* Alpha ECOFF and ELF relocations. Some of these treat the symbol or
"addend" in some special way.
/* This is a 16 bit offset from the zero data area pointer, with the
bits placed non-contigously in the instruction. */
BFD_RELOC_V850_ZDA_16_16_SPLIT_OFFSET,
+
+/* This is a 6 bit offset from the call table base pointer. */
+ BFD_RELOC_V850_CALLT_6_7_OFFSET,
+
+/* This is a 16 bit offset from the call table base pointer. */
+ BFD_RELOC_V850_CALLT_16_16_OFFSET,
/* end-sanitize-v850e */