-/* DO NOT EDIT! -*- buffer-read-only: t -*- This file is automatically
- generated from "bfd-in.h", "init.c", "opncls.c", "libbfd.c",
- "bfdio.c", "bfdwin.c", "section.c", "archures.c", "reloc.c",
- "syms.c", "bfd.c", "archive.c", "corefile.c", "targets.c", "format.c",
+/* DO NOT EDIT! -*- buffer-read-only: t -*- This file is automatically
+ generated from "bfd-in.h", "init.c", "opncls.c", "libbfd.c",
+ "bfdio.c", "bfdwin.c", "section.c", "archures.c", "reloc.c",
+ "syms.c", "bfd.c", "archive.c", "corefile.c", "targets.c", "format.c",
"linker.c" and "simple.c".
Run "make headers" in your build bfd/ to regenerate. */
/* Nonzero if this section needs the relax finalize pass. */
unsigned int need_finalize_relax:1;
+ /* Nonzero if this section has a gp reloc. */
+ unsigned int has_gp_reloc:1;
+
/* Usused bits. */
- unsigned int flag12:1;
unsigned int flag13:1;
unsigned int flag14:1;
unsigned int flag15:1;
#define bfd_mach_h8300hn 4
#define bfd_mach_h8300sn 5
#define bfd_mach_h8300sx 6
+#define bfd_mach_h8300sxn 7
bfd_arch_pdp11, /* DEC PDP-11 */
bfd_arch_powerpc, /* PowerPC */
#define bfd_mach_ppc 32
#define bfd_mach_msp43 43
#define bfd_mach_msp44 44
#define bfd_mach_msp15 15
-#define bfd_mach_msp16 16
+#define bfd_mach_msp16 16
bfd_arch_xtensa, /* Tensilica's Xtensa cores. */
#define bfd_mach_xtensa 1
bfd_arch_last
BFD_RELOC_XTENSA_OP1,
BFD_RELOC_XTENSA_OP2,
-/* Xtensa relocation to mark that the assembler expanded the
+/* Xtensa relocation to mark that the assembler expanded the
instructions from an original target. The expansion size is
encoded in the reloc size. */
BFD_RELOC_XTENSA_ASM_EXPAND,
-/* Xtensa relocation to mark that the linker should simplify
-assembler-expanded instructions. This is commonly used
-internally by the linker after analysis of a
+/* Xtensa relocation to mark that the linker should simplify
+assembler-expanded instructions. This is commonly used
+internally by the linker after analysis of a
BFD_RELOC_XTENSA_ASM_EXPAND. */
BFD_RELOC_XTENSA_ASM_SIMPLIFY,
BFD_RELOC_UNUSED };