* configure.ac: Add Microblaze target.

[deliverable/binutils-gdb.git] / bfd / cpu-ia64-opc.c

diff --git a/bfd/cpu-ia64-opc.c b/bfd/cpu-ia64-opc.c
index 12a13c0c5ebb847c126907a2769a655b83691bb9..10dc2aaee3f35cd2f5650e493e4981a7ad809e65 100644 (file)
--- a/bfd/cpu-ia64-opc.c
+++ b/bfd/cpu-ia64-opc.c
@@ -1,22 +1,23 @@
-/* Copyright 1998, 1999, 2000, 2001, 2002, 2003
+/* Copyright 1998, 1999, 2000, 2001, 2002, 2003, 2005, 2006, 2007
    Free Software Foundation, Inc.
    Contributed by David Mosberger-Tang <davidm@hpl.hp.com>
 
-This file is part of BFD, the Binary File Descriptor library.
+   This file is part of BFD, the Binary File Descriptor library.
 
-This program is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2 of the License, or
-(at your option) any later version.
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
 
-This program is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
 
-You should have received a copy of the GNU General Public License
-along with this program; if not, write to the Free Software
-Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02110-1301, USA.  */
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+   MA 02110-1301, USA.  */
 
 /* Logically, this code should be part of libopcode but since some of
    the operand insertion/extraction functions help bfd to implement
@@ -113,6 +114,29 @@ ext_immu (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep)
   return 0;
 }
 
+static const char*
+ins_immu5b (const struct ia64_operand *self, ia64_insn value,
+           ia64_insn *code)
+{
+  if (value < 32 || value > 63)
+    return "value must be between 32 and 63";
+  return ins_immu (self, value - 32, code);
+}
+
+static const char*
+ext_immu5b (const struct ia64_operand *self, ia64_insn code,
+           ia64_insn *valuep)
+{
+  const char *result;
+
+  result = ext_immu (self, code, valuep);
+  if (result)
+    return result;
+
+  *valuep = *valuep + 32;
+  return 0;
+}
+
 static const char*
 ins_immus8 (const struct ia64_operand *self, ia64_insn value, ia64_insn *code)
 {
@@ -457,6 +481,10 @@ const struct ia64_operand elf64_ia64_operands[IA64_OPND_COUNT] =
     { REG, ins_reg,   ext_reg,  "r", {{ 2, 20}}, 0,            /* R3_2 */
       "a general register r0-r3" },
 
+    /* memory operands: */
+    { IND, ins_reg,   ext_reg, "",      {{7, 20}}, 0,          /* MR3 */
+      "a memory address" },
+
     /* indirect operands: */
     { IND, ins_reg,   ext_reg, "cpuid", {{7, 20}}, 0,          /* CPUID_R3 */
       "a cpuid register" },
@@ -468,8 +496,6 @@ const struct ia64_operand elf64_ia64_operands[IA64_OPND_COUNT] =
       "an itr register" },
     { IND, ins_reg,   ext_reg, "ibr",   {{7, 20}}, 0,          /* IBR_R3 */
       "an ibr register" },
-    { IND, ins_reg,   ext_reg, "",      {{7, 20}}, 0,          /* MR3 */
-      "an indirect memory address" },
     { IND, ins_reg,   ext_reg, "msr",   {{7, 20}}, 0,          /* MSR_R3 */
       "an msr register" },
     { IND, ins_reg,   ext_reg, "pkr",   {{7, 20}}, 0,          /* PKR_R3 */
@@ -504,6 +530,8 @@ const struct ia64_operand elf64_ia64_operands[IA64_OPND_COUNT] =
       "a 1-bit integer (-1, 0)" },
     { ABS, ins_immu,  ext_immu,  0, {{ 2, 13}}, UDEC,          /* IMMU2 */
       "a 2-bit unsigned (0-3)" },
+    { ABS, ins_immu5b,  ext_immu5b,  0, {{ 5, 14}}, UDEC,      /* IMMU5b */
+      "a 5-bit unsigned (32 + (0-31))" },
     { ABS, ins_immu,  ext_immu,  0, {{ 7, 13}}, 0,             /* IMMU7a */
       "a 7-bit unsigned (0-127)" },
     { ABS, ins_immu,  ext_immu,  0, {{ 7, 20}}, 0,             /* IMMU7b */